A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits with Dynamic and Static C-elements

  • Pradeep Kumar BiswalEmail author
  • Santosh Biswas


The fast growing in complexity of digital VLSI circuits with the advance of deep sub-micron scaling causes occurrence of faults during normal operation of the circuits. These faults cannot be detected by off-line test or Built-In-Self-Test (BIST) techniques. Further, a number of critical faults may require detection at the functional mode during run-time. On-line Testing (OLT) provides a solution to both the problems, and can be implemented using appropriate Design-for-Testability (DFT) techniques. Nowadays, use of asynchronous circuits in semiconductor industry has rapidly increased because of no clock skew problem, low power consumption, average case performances and high degree of modularity. It has been found in the literature of OLT of VLSI circuits that the number of OLT schemes proposed for asynchronous circuits is very few compared to synchronous circuits. The main drawbacks of the existing OLT schemes for asynchronous circuits are protocol dependency, high area overhead and scalability. In this work, we have proposed a partial replication based OLT scheme for asynchronous circuits with dynamic and static C-elements using Binary Decision Diagram (BDD). The proposed scheme works for all circuits irrespective of their design protocols and achieves high fault coverage and comparatively low area overhead. It has been observed that the area overhead is further reduced with increase in values of FD-transitions (Fault Detecting transitions) exclusion. Furthermore, the use of BDD enables the scheme to handle fairly large circuits.


On-line testing (OLT) Asynchronous circuit Binary decision diagram (BDD) Area overhead (AO) Fault coverage (FC) Signal transition graph (STG) 



  1. 1.
    Al-Asaad H (2010) Efficient techniques for reducing error latency in on-line periodic built-in self-test. IEEE Instrum Meas Mag 13(4):28–32CrossRefGoogle Scholar
  2. 2.
    Balasubrahamanyam Y, Chowdary G L, Subrahmanyam T J V S (2012) A novel low power pattern generation technique for concurrent BIST architecture. International Journal Computer Technology and Applications 3(2):561–565Google Scholar
  3. 3.
    Balasubramanian A, Bhuva BL, Massengill LW, Narasimham B, Shuler RL, Loveless TD, Holman WT (2008) A built-in self-test (BIST) technique for single-event testing in digital circuits. IEEE Trans Nucl Sci 6 (55):3130–3135CrossRefGoogle Scholar
  4. 4.
    Biswal P K, Biswas S (2015) Timed discrete event system approach to online testing of asynchronous circuits. In: Mediterranean conference on control and automation (MED), pp 341–348Google Scholar
  5. 5.
    Biswal P K, Sambho H P, Biswas S (2016) A discrete event system approach to on-line testing of digital circuits with measurement limitation. Engineering Science and Technology, an International Journal, Elsevier 19 (3):1473–1487CrossRefGoogle Scholar
  6. 6.
    Biswal PK, Biswas S (2015) A binary decision diagram based on-line testing of digital vlsi circuits for feedback bridging faults. Microelectron J Elsevier 46(7):598–616CrossRefGoogle Scholar
  7. 7.
    Biswal PK, Biswas S (2017) On-line testing of digital vlsi circuits at register transfer level using high level decision diagrams. Microelectron J 67(C):88–100CrossRefGoogle Scholar
  8. 8.
    Biswas PK, Biswal S, Mishra K, Kapoor HK (2015) A discrete event system approach to online testing of speed independent circuits. VLSI Des 2015(651785):16Google Scholar
  9. 9.
    Biswas S, Mukhopadhyay S, Patra A (2005) A formal approach to on-line monitoring of digital VLSI circuits: theory, design and implementation. J Electron Test, Springer 21(5):503–537CrossRefGoogle Scholar
  10. 10.
    Brand D (1993) Verification of large synthesized designs. In: Proceedings of international conference on computer aided design (ICCAD), pp 534–537Google Scholar
  11. 11.
    Bryant RE (1992) Symbolic boolean manipulation with ordered binary-decision diagrams. ACM Comput Surv 24(3):293–318MathSciNetCrossRefGoogle Scholar
  12. 12.
    Bushnell M, Agrawal V (2006) Essentials of electronic testing for digital memory and mixed-signal VLSI circuits, volume 17 Springer Science and Business MediaGoogle Scholar
  13. 13.
    Chen Y-Y (2005) Concurrent detection of control flow errors by hybrid signature monitoring. IEEE Trans Comput 54(10):1298–1313CrossRefGoogle Scholar
  14. 14.
    Das N, Roy P, Rahaman H (2013) Built-in-self-test technique for diagnosis of delay faults in cluster-based field programmable gate arrays. IET Comput Digit Tech 7(5):210–220CrossRefGoogle Scholar
  15. 15.
    Drineas P, SPaRre YM (2003) Selective partial replication for concurrent fault-detection in fsm s. IEEE Trans Instrum Meas 52(6):1729–1737CrossRefGoogle Scholar
  16. 16.
    Fišer P, Kubalík P, Kubátová H (2008) An efficient multiple-parity generator design for on-line testing on FPGA. In Euromicro conference on digital system design architectures, Methods and tools, pp 96–99Google Scholar
  17. 17.
    Gopal P, Biswas S, Manda C, Bhattacharya BB (2010) A BDD-based approach to design power-aware on-line detectors for digital circuits. In: International SOC conference (SOCC), pp 343–346. IEEEGoogle Scholar
  18. 18.
    Hodges DA et al (2005) Analysis and design of digital integrated circuits. In: Deep submicron technology (special Indian Edition). Tata McGraw-Hill EducationGoogle Scholar
  19. 19.
    Hulgaard H, Burns SM, Borriello G (1995) Testing asynchronous circuits: A survey. Integration, The VLSI journal Elsevier 19(3):111–131CrossRefGoogle Scholar
  20. 20.
    Myers CJ (2004) Asynchronous circuit design. John Wiley and SonsGoogle Scholar
  21. 21.
    Nicolaidis M, Zorian Y (1998) On-line testing for VLSI– a compendium of approaches. J Electron Test, Springer 12(1-2):7–20CrossRefGoogle Scholar
  22. 22.
    Perdu P (2010) Life issues, robustness consequences and reliability challenges for very deep sub micron technologies. In: Asia-pacific international symposium on electromagnetic compatibility, pp 1014–1019Google Scholar
  23. 23.
    Petrify: a tool for synthesis of petri nets and asynchronous circuits., 1999
  24. 24.
    Sen B, Das J, Sikdar BK (2012) A DFT methodology targeting online testing of reversible circuit. In: International conference on devices, circuits and systems, pp 689–693Google Scholar
  25. 25.
    Shang D, Bystrov A, Yakovlev A, Koppad D (2005) On-line testing of globally asynchronous circuits. In: International on-line testing symposium, pp 135–140Google Scholar
  26. 26.
    Shang D, Yakovlev A, Burnsand F P, Xia F, Bystrov A (2006) Low-cost online testing of asynchronous handshakes. In: European test symposium, pp 225–232Google Scholar
  27. 27.
    Tan L, Tan Y, Xu J (2013) CFEDR Control-flow error detection and recovery using encoded signatures monitoring. In: International symposium on defect and fault tolerance in VLSI and nanotechnology systems, pp 25–32Google Scholar
  28. 28.
    Trevisan Moreira M, Gehm Moraes F, Vilar Calazans N L (2014) Beware the dynamic c-element. IEEE Trans Very Large Scale Integr VLSI Syst 22(7):1644–1647CrossRefGoogle Scholar
  29. 29.
    Verdel T, Yiorgos M (2002) Duplication-based concurrent error detection in asynchronous circuits Shortcomings and remedies. In: International symposium on defect and fault-tolerance in VLSI systems, pp 345–353Google Scholar
  30. 30.
    Voyiatzis I, Paschalis A, Gizopoulos D, Halatsis C, Makri F S, Hatzimihail M (2008) An input vector monitoring concurrent BIST architecture based on a precomputed test set. IEEE Trans Comput 57(8):1012–1022MathSciNetCrossRefGoogle Scholar

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Authors and Affiliations

  1. 1.Department of Computer Science and EngineeringIIIT BhagalpurBiharIndia
  2. 2.Department of Electrical Engineering and Computer ScienceIIT BhilaiBiharIndia

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