Advertisement

Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing

  • Dilip Kumar MaityEmail author
  • Surajit Kumar Roy
  • Chandan Giri
Article
  • 12 Downloads

Abstract

Three-dimensional Integrated Circuits (3D ICs) based on Through-Silicon Vias (TSVs) provide many benefits, such as high density, high bandwidth and low-power consumption. However, defects in TSV due to complex fabrication steps decrease the yield and reliability of 3D ICs. Therefore each die should be tested before it is stacked through pre-bond test. Pre-bond test and defect identification of TSVs are extremely important to screen out defective TSVs early in the manufacturing flow. Also, test cost minimization is one of the key issues of the testing process. The existing test time minimization solutions for pre-bond test consider random TSV defects. However, in practice clustered TSV faults are quite common. In this paper, we propose a novel test time minimization technique to address both random and clustered defect distributions. The proposed solutions are based on recursive bi-partitioning and padding of test sessions to minimize the number of required test sessions as well as test time. Simulation results show that the proposed method can achieve more than 50% reduction in test time for a 20-TSV network with four faulty TSVs compared to serial testing approach. The proposed algorithm also pinpoints the defective TSVs in a TSV network with a reduced test time compared to prior works.

Keywords

3D IC Pre-bond testing Random defects Clustered defects TSV test 

Notes

References

  1. 1.
    Chen P-Y, Wu C-W, Kwai D-M (2009) On-chip tsv testing for 3d ic before bonding using sense amplification. In: 2009 Asian test symposium. IEEE, pp 450–455Google Scholar
  2. 2.
    Chen H, Shih J, Li S, Lin H, Wang M, Peng C (2010) Electrical tests for three-dimensional ics (3dics) with tsvs. In: International test conference 3D-test workshop, pp 1–6Google Scholar
  3. 3.
    Chen P-Y, Wu C-W, Kwai D-M (2010) On-chip testing of blind and open-sleeve tsvs for 3d ic before bonding. In: 2010 28th VLSI test symposium (VTS). IEEE, pp 263–268Google Scholar
  4. 4.
    Cho M, Liu C, Kim DH, Lim SK, Mukhopadhyay S (2010) Design method and test structure to characterize and repair tsv defect induced signal degradation in 3d system. In: 2010 IEEE/ACM international conference on computer-aided design (ICCAD). IEEE, pp 694–697Google Scholar
  5. 5.
    Cho M, Liu C, Kim DH, Lim SK, Mukhopadhyay S (2011) Pre-bond and post-bond test and signal recovery structure to characterize and repair tsv defect induced signal degradation in 3-d system. IEEE Trans Comp Packag Manuf Technol 1(11):1718–1727CrossRefGoogle Scholar
  6. 6.
    Davis WR, Wilson J, Mick S, Xu J, Hua H, Mineo C, Sule AM, Steer M, Franzon P (2005) Demystifying 3d ics: the pros and cons of going vertical. IEEE Des Test Comput 22(6):498–510CrossRefGoogle Scholar
  7. 7.
    Deutsch S, Chakrabarty K (2014) Contactless pre-bond tsv test and diagnosis using ring oscillators and multiple voltage levels. IEEE Trans Comput-Aided Des Integr Circ Syst 33(5):774–785CrossRefGoogle Scholar
  8. 8.
    Dukovic J, Ramaswami S, Pamarthy S, Yalamanchili R, Rajagopalan N, Sapre K, Cao Z, Ritzdorf T, Wang Y, Eaton B, Ding R, Hernandez M, Naik M, Mao D, Tseng J, Cui D, Mori G, Fulmer P, Sirajuddin K, Hua J, Xia S, Erickson D, Beica R, Young E, Kusler P, Kulzer R, Oemardani S, Dai H, Xu X, Okazaki M, Dotan K, Yu C, Lazik C, Tran J, Luo L (2010) Through-silicon-via technology for 3D integration. In: IEEE International memory workshop, pp 1–2Google Scholar
  9. 9.
    Hsieh A-C, Hwang T (2011) Tsv redundancy: architecture and design issues in 3-d ic. IEEE Trans Very Large Scale Integr (VLSI) Syst 20(4):711–722CrossRefGoogle Scholar
  10. 10.
    Huang Y-J, Li J-F, Chen J-J, Kwai D-M, Chou Y-F, Wu C-W (2011) A built-in self-test scheme for the post-bond test of tsvs in 3d ics. In: 29th VLSI test symposium. IEEE, pp 20–25Google Scholar
  11. 11.
    Huang S-Y, Lin Y-H, Tsai K-HH, Cheng W-T, Sunter S, Chou Y-F, Kwai D-M (2012) Small delay testing for tsvs in 3-d ics. In: Proceedings of the 49th annual design automation conference. ACM, pp 1031–1036Google Scholar
  12. 12.
    Huang L-R, Huang S-Y, Sunter S, Tsai K-H, Cheng W-T (2013) Oscillation-based prebond tsv test. IEEE Trans Comput-Aided Des Integr Circ Syst 32(9):1440–1444CrossRefGoogle Scholar
  13. 13.
    Lee H-HS, Chakrabarty K (2009) Test challenges for 3d integrated circuits. IEEE Des Test Comput 26 (5):26–35CrossRefGoogle Scholar
  14. 14.
    Marinissen EJ, Chi C-C, Konijnenburg M, Verbree J (2012) A dft architecture for 3d-sics based on a standardizable die wrapper. J Electron Test 28(1):73–92CrossRefGoogle Scholar
  15. 15.
    Meyer FJ, Pradhan DK (1989) Modeling defect spatial distribution. IEEE Trans Comput 38(4):538–546CrossRefGoogle Scholar
  16. 16.
    Nain RK, Pinge S, Chrzanowska-Jeske M (2010) Yield improvement of 3d ics in the presence of defects in through signal vias. In: 2010 11th International symposium on quality electronic design (ISQED). IEEE, pp 598–605Google Scholar
  17. 17.
    Noia B, Chakrabarty K (2011) Identification of defective tsvs in pre-bond testing of 3d ics. In: 2011 Asian test symposium. IEEE, pp 187–194Google Scholar
  18. 18.
    Noia B, Chakrabarty K (2011) Pre-bond probing of tsvs in 3d stacked ics. In: 2011 IEEE international test conference. IEEE, pp 1–10Google Scholar
  19. 19.
    Noia B, Chakrabarty K (2014) Design-for-test and test optimization techniques for TSV-based 3D stacked ICs. SpringerGoogle Scholar
  20. 20.
    Pasca V, Anghel L, Benabdenbi M (2011) Configurable thru-silicon-via interconnect built-in self-test and diagnosis. In: 2011 12th Latin American test workshop (LATW). IEEE, pp 1–6Google Scholar
  21. 21.
    Roy SK, Chatterjee S, Giri C (2012) Identifying faulty tsvs in 3d stacked ic during pre-bond testing. In: 2012 International symposium on electronic system design (ISED). IEEE, pp 162–166Google Scholar
  22. 22.
    Roy SK, Chatterjee S, Giri C, Rahaman H (2013) Faulty tsvs identification and recovery in 3d stacked ics during pre-bond testing. In: 2013 IEEE international 3D systems integration conference (3DIC). IEEE, pp 1–6Google Scholar
  23. 23.
    Schaper LW, Burkett SL, Spiesshoefer S, Vangara GV, Rahman Z, Polamreddy S (2005) Architectural implications and process development of 3-d vlsi z-axis interconnects using through silicon vias. IEEE Trans Adv Packag 28(3):356–366CrossRefGoogle Scholar
  24. 24.
    Smith K, Hanaway P, Jolley M, Gleason R, Strid E, Daenen T, Dupas L, Knuts B, Marinissen EJ, Van Dievel M (2011) Evaluation of tsv and micro-bump probing for wide i/o testing. In: 2011 IEEE international test conference. IEEE, pp 1–10Google Scholar
  25. 25.
    Stapper CH (1986) On yield, fault distributions, and clustering of particles. IBM J Res Dev 30(3):326–338CrossRefGoogle Scholar
  26. 26.
    Stapper CH, Armstrong FM, Saji K (1983) Integrated circuit yield statistics. Proc IEEE 71(4):453–470CrossRefGoogle Scholar
  27. 27.
    Swinnen B, Ruythooren W, De Moor P, Bogaerts L, Carbonell L, De Munck K, Eyckens B, Stoukatch S, Tezcan DS (2006) Z. Tokei others, 3d integration by cu-cu thermo-compression bonding of extremely thinned bulk-si die containing 10 μ m pitch through-si vias. In: 2006 International electron devices meeting. IEEE, pp 1–4Google Scholar
  28. 28.
    Tahoori MB (2005) Defects, yield, and design in sublithographic nano-electronics. In: 20th IEEE international symposium on defect and fault tolerance in VLSI systems (DFT’05). IEEE, pp 3–11Google Scholar
  29. 29.
    Topol AW, La Tulipe D, Shi L, Alam S, Frank D, Steen S, Vichiconti J, Posillico D, Cobb M, Medd S et al (2005) Enabling soi-based assembly technology for three-dimensional (3d) integrated circuits (ics). In: IEEE International electron devices meeting, 2005 IEDM technical digest. IEEE, pp 352–355Google Scholar
  30. 30.
    Tsai M, Klooz A, Leonard A, Appel J, Franzon P (2009) Through silicon via (tsv) defect/pinhole self test circuit for 3d-ic. In: 2009 IEEE International conference on 3D system integration. IEEE, pp 1–8Google Scholar
  31. 31.
    Wang C, Zhou J, Zhao B, Liu X, Royannez P, Je M (2012) Self-test methodology and structures for pre-bond tsv testing in 3d-ic system. In: 2012 IEEE Asian solid state circuits conference (A-SSCC). IEEE, pp 393–396Google Scholar
  32. 32.
    Zhang B, Agrawal VD (2014) An optimal probing method of pre-bond tsv fault identification in 3d stacked ics. In: 2014 SOI-3D-subthreshold microelectronics technology unified conference (S3S). IEEE, pp 1–3Google Scholar
  33. 33.
    Zhang B, Agrawal VD (2014) An optimized diagnostic procedure for pre-bond tsv defects. In: 2014 IEEE 32nd international conference on computer design (ICCD). IEEE, pp 189–194Google Scholar
  34. 34.
    Zhang B, Agrawal VD (2015) Diagnostic tests for pre-bond tsv defects. In: 2015 28th International conference on VLSI design. IEEE, pp 387–392Google Scholar
  35. 35.
    Zhao Y, Khursheed S, Al-Hashimi BM (2011) Cost-effective tsv grouping for yield improvement of 3d-ics. In: 2011 Asian test symposium. IEEE, pp 201–206Google Scholar
  36. 36.
    Zhao Y, Khursheed S, Al-Hashimi BM (2014) Online fault tolerance technique for tsv-based 3-d-ic. IEEE Trans Very Large Scale Integr (VLSI) Syst 23(8):1567–1571CrossRefGoogle Scholar
  37. 37.
    Zimouche H, Di Natale G, Flottes M-l, Rouzeyre B (2013) A bist method for tsvs pre-bond test. In: 2013 8th IEEE design and test symposium. IEEE, pp 1–6Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  • Dilip Kumar Maity
    • 1
    Email author
  • Surajit Kumar Roy
    • 2
  • Chandan Giri
    • 2
  1. 1.Department of Computer Science and EngineeringAcademy of TechnologyAdisaptagramIndia
  2. 2.Department of Information TechnologyIndian Institute of Engineering Science and TechnologyShibpurIndia

Personalised recommendations