Low Delay 3-Bit Burst Error Correction Codes
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The increasing importance of Multiple Cell Upsets (MCUs) in modern memories has spurred research on error correction codes that can correct adjacent bit errors. For example, Double Adjacent Error Correction (DAEC), 3-bit burst and 4-bit burst codes have been proposed in the last years. However, as the error correction capabilities are increased so is the complexity of the encoder and decoder circuits. This directly impacts the encoding and decoding delay and thus limits the use of the codes in high speed memories. To reduce the complexity, some techniques have been proposed recently. Those include more advanced optimization programs to find codes with a lower number of ones in the parity check matrix or the interleaving of data and parity check bits to simplify the decoding. In this paper, those techniques are combined to design more efficient 3-bit burst error correction codes. The encoders and decoders for the proposed codes have been implemented and compared with the state of the art 3-bit burst error correction codes. The results show that the new codes reduce the encoder and decoder delay significantly. Therefore, the proposed codes provide memory designers with a more efficient option to implement protection against 3-bit burst errors for high speed memories.
KeywordsSoft errors MCU Memories Error correction codes
This work is supported by the Fundamental Research Funds for the Central Universities (Grant No.HIT.KISTP.201404), Harbin science and innovation research special fund (2015RAXXJ003), and Special found for development of Shenzhen strategic emerging industries (JCYJ20150625142543456). Pedro Reviriego was with Universidad Antonio de Nebrija at the time of writing the initial draft of this paper and would like to acknowledge the support of the TEXEO project TEC2016-80339-R funded by the Spanish Ministry of Economy and Competitivity.
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