Advertisement

Low Delay 3-Bit Burst Error Correction Codes

  • Jiaqiang Li
  • Pedro Reviriego
  • Liyi XiaoEmail author
Article
  • 15 Downloads

Abstract

The increasing importance of Multiple Cell Upsets (MCUs) in modern memories has spurred research on error correction codes that can correct adjacent bit errors. For example, Double Adjacent Error Correction (DAEC), 3-bit burst and 4-bit burst codes have been proposed in the last years. However, as the error correction capabilities are increased so is the complexity of the encoder and decoder circuits. This directly impacts the encoding and decoding delay and thus limits the use of the codes in high speed memories. To reduce the complexity, some techniques have been proposed recently. Those include more advanced optimization programs to find codes with a lower number of ones in the parity check matrix or the interleaving of data and parity check bits to simplify the decoding. In this paper, those techniques are combined to design more efficient 3-bit burst error correction codes. The encoders and decoders for the proposed codes have been implemented and compared with the state of the art 3-bit burst error correction codes. The results show that the new codes reduce the encoder and decoder delay significantly. Therefore, the proposed codes provide memory designers with a more efficient option to implement protection against 3-bit burst errors for high speed memories.

Keywords

Soft errors MCU Memories Error correction codes 

Notes

Acknowledgments

This work is supported by the Fundamental Research Funds for the Central Universities (Grant No.HIT.KISTP.201404), Harbin science and innovation research special fund (2015RAXXJ003), and Special found for development of Shenzhen strategic emerging industries (JCYJ20150625142543456). Pedro Reviriego was with Universidad Antonio de Nebrija at the time of writing the initial draft of this paper and would like to acknowledge the support of the TEXEO project TEC2016-80339-R funded by the Spanish Ministry of Economy and Competitivity.

References

  1. 1.
    Chen CL, Hsiao MY (1984) Error-correcting codes for semiconductor memory applications: a state-of-the-art review. IBM J Res Dev 28:124–134.  https://doi.org/10.1147/rd.282.0124 CrossRefGoogle Scholar
  2. 2.
    Dutta A, Touba NA (2007) Multiple bit upset tolerant memory using a selective cycle avoidance based SEC-DED-DAEC Code. In: Proceedings of the IEEE VLSI test symmposium, pp 349–354.  https://doi.org/10.1109/VTS.2007.40
  3. 3.
    Fujiwara E (2006) Code design for dependable systems: theory and practical application. Wiley, New JerseyCrossRefzbMATHGoogle Scholar
  4. 4.
    Harada R, Abe S, Fuketa H, Uemura T, Hashimoto M, Watanabe Y (2012) Angular dependency of neutron-induced multiple cell upsets in 65-nm 10T subthreshold SRAM. IEEE Trans Nucl Sci 59:2791–2795.  https://doi.org/10.1109/TNS.2012.2224373 CrossRefGoogle Scholar
  5. 5.
    Hsiao MY (1970) A class of optimal minimum odd-weight-column SEC-DED codes. IBM J Res Dev 14:395–401.  https://doi.org/10.1147/rd.144.0395 CrossRefGoogle Scholar
  6. 6.
    Ibe E, Taniguchi H, Yahagi Y, Shimbo K, Toba T (2010) Impact of scaling on neutron-induced soft error in SRAMs from a 250 nm to a 22 nm design rule. IEEE Trans Electron Dev 57:1527–1538.  https://doi.org/10.1109/TED.2010.2047907 CrossRefGoogle Scholar
  7. 7.
    Kanekawa N, Ibe E, Suga T, Uematsu Y (2011) Dependability in electronic systems. Springer, New YorkCrossRefGoogle Scholar
  8. 8.
    Li J, Reviriego P, Xiao L, Argyrides C, Li J (2018) Extending 3-bit burst error-correction codes with quadruple adjacent error correction. IEEE Trans Very Large Scale Integr Syst (VLSI) 26:221–229.  https://doi.org/10.1109/TVLSI.2017.2766361 CrossRefGoogle Scholar
  9. 9.
    Neale A, Sachdev M (2016) Neutron radiation induced soft error rates for an adjacent-ECC protected SRAM in 28 nm CMOS. IEEE Trans Nucl Sci 63:1912–1917.  https://doi.org/10.1109/TNS.2016.2547963 CrossRefGoogle Scholar
  10. 10.
    Reviriego P, Maestro JA, Baeg S, Wen S, Wong R (2010) Protection of memories suffering MCUs through the selection of the optimal interleaving distance. IEEE Trans Nucl Sci 57:2124–2128.  https://doi.org/10.1109/TNS.2010.2042818 CrossRefGoogle Scholar
  11. 11.
    Reviriego P, Liu S, Xiao L, Maestro JA (2016) An efficient single and double-adjacent error correcting parallel decoder for the (24,12) extended golay code. IEEE Trans Very Large Scale Integr Syst (VLSI) 24:1603–1606.  https://doi.org/10.1109/TVLSI.2015.2465846 CrossRefGoogle Scholar
  12. 12.
    Saiz-Adalid L, Reviriego P, Gil P, Pontarelli S, Maestro JA (2015) MCU tolerance in SRAMs through low-redundancy triple adjacent error correction. IEEE Trans Very Large Scale Integr (VLSI) Syst 23:2332–2336.  https://doi.org/10.1109/TVLSI.2014.2357476 CrossRefGoogle Scholar
  13. 13.
    Satoh S, Tosaka Y, Wender SA (2000) Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAM’s. IEEE Electron Dev Lett 21:310–312.  https://doi.org/10.1109/55.843160 CrossRefGoogle Scholar
  14. 14.
    Tsiligiannis G et al (2013) Multiple-cell-upsets on a commercial 90nm SRAM in dynamic mode. In: Proceedings of the 14th European conference on radiation and its effects on components and systems (RADECS).  https://doi.org/10.1109/RADECS.2013.6937429

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Harbin Institute of TechnologyHarbinChina
  2. 2.Universidad Carlos III de MadridMadridSpain

Personalised recommendations