Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits
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As the feature size of CMOS transistors scales down, Single Event Transient (SET) has been an important consideration in designing modern radiation tolerant circuits because it may cause some failures in the circuit outputs. Many researches have been done in analyzing the impact of SET on nanometer CMOS circuits. However, it is difficult to consider numerous factors such as three fault masking effects, consecutive cycles, signal correlations and so on. In this paper, we have presented a new approach for analyzing the propagation probabilities of SET in logic circuits. All three fault masking effects have been considered uniformly and SET Propagation Probabilities Matrices (SPPMs) have been used to represent the SET Propagation Probabilities (SPPs) in current clock cycle. Based on the matrix union operations which we have defined, the SPPs in consecutive cycles can be calculated accurately and efficiently. Experimental results on ISCAS’89 benchmark circuits show that our approach is practicable.
KeywordsSingle event transient (SET) Propagation probability matrix Masking effect Matrix union operation Logic circuits
This research was supported in part by the National Natural Science Foundation of China (NSFC) under grant No.61702052, 61504013, in part by the Scientific Research Fund of Hunan Provincial Education Department under grant No.18A137, 17B011 and in part by the Open Research Fund of Hunan Provincial Key Laboratory of Intelligent Processing of Big Data on Transportation.
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