Advertisement

RTOS Solution for NoC-Based COTS MPSoC Usage in Mixed-Criticality Systems

  • Serhiy AvramenkoEmail author
  • Massimo Violante
Article
First Online:
  • 23 Downloads

Abstract

Multi-core system on chip (MPSoC) is a clear trend for the future embedded systems. Network-on-chip (NoC) is the most scalable interconnection, allowing to have hundreds of cores on the same chip. On the other hand, safety critical applications (e.g., avionic) require the system to present a set of strict guarantees, which are difficult to achieve for MPSoC-based systems. In this work we target Commercial Off-The-Shelf (COTS) NoC-based MPSoC for the mixed criticality systems, in the safety critical field. The focus of the proposed work is on the issue of contention on the NoC and the related temporal interference. As the main contribution, we propose a partitioning technique to enable the usage of COTS NoC-based MPSoC for the mixed criticality systems, enabling an unbounded number of levels of criticality to be deployed. The proposed technique exploits the deterministic routing algorithm of the NoC and it is suitable for any NoC-based MPSoC which meets a set of fairly common characteristics. The partitioning technique is intended to have a purely software implementation as a module of a real-time operating system, which will allow easier certification as well. The proposed approach overcomes the concept of strict network partitioning between regions, as it implements traffic isolation allowing partitions to overlap. As a further contribution this paper describes the cost of proposed solution in terms of the network connectivity reduction. A set of rules to enable an efficient usage of the proposed solution has been provided.

Keywords

Network-on-chip Mixed-criticality systems Commercial-off-the-shelf Real-time operating system Multi-core Avionics 
This is a preview of subscription content, log in to check access.

Notes

References

  1. 1.
    (1996) ARP4761 - Guidelines and methods for conducting the safety assessment process on civil airborne systems and equipment. SAE InternationalGoogle Scholar
  2. 2.
    (2000) RTCA/DO-254 Design Assurance Guidance for Airborne Electronic Hardware. RTCA IncorporatedGoogle Scholar
  3. 3.
    (2000) IEC-61508. Functional safety of electrical/electronic/programmable electronic safety related systems. International Electrotechnical CommissionGoogle Scholar
  4. 4.
    (2003) ARINC 653–1 avionics application software standard interface. Technical report. ARINCGoogle Scholar
  5. 5.
    (2010) IEEE Std 1228–1994 – IEEE Standard for Software Safety Plans. Institute of Electrical and Electronics EngineersGoogle Scholar
  6. 6.
    (2011) ISO 26262, Road Vehicles - Functional Safety. International Organization for Standardization (ISO)Google Scholar
  7. 7.
    (2012) DO-178C/ED-12C software considerations in airborne systems and equipment certification. RTCA, IncorporatedGoogle Scholar
  8. 8.
    (2015) Tile Processor Architecture Overview for the TILEPro Series, Tilera Corporation, http://www.mellanox.com/repository/solutions/tile-scm/docs/UG120-Architecture-Overview-TILEPro.pdf. Accessed 12 June 2017
  9. 9.
    Ahmadian H, Obermaisser R (2015) Time-triggered extension layer for on-chip network interfaces in mixed-criticality systems. In Proc. 18th Euromicro Conf. Digit. Syst. Des (DSD), pp. 693–699Google Scholar
  10. 10.
    Anderson J, Baruah B, Brandenburg B (2009) Multicore operating-system support for mixed criticality. In Proc. Workshop on Mixed Criticality: Roadmap to Evolving UAV CertificationGoogle Scholar
  11. 11.
    Avramenko S, Esposito S, Violante M, et al (2015) An hybrid architecture for consolidating mixed criticality applications on multicore systems. In Proc. IEEE 21st Intl On-Line Testing Symp (IOLTS), pp. 26–29Google Scholar
  12. 12.
    Azad SP, Niazmand B, Janson K, George N, Oyeniran AS (2017) From Online Fault Detection to Fault Management in Network-on-Chips: A Ground-Up Approach. In Proc. Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp. 48–53Google Scholar
  13. 13.
    Becker M, et al (2016) Contention-free execution of automotive applications on a clustered many-core platform. In Proc. 26th Euromicro Conference on Real-Time Systems (ECRTS), pp. 14–24Google Scholar
  14. 14.
    Boniol F, Cassé H, Noulard E, Pagetti C (2012) Deterministic execution model on COTS hardware. Lect Notes Comput Sci (including Subser Lect Notes Artif Intell Lect Notes Bioinformatics), vol 7179 LNCS, pp. 98–110Google Scholar
  15. 15.
    Bortolon FT, Abich G, Bampi S, Reis R, Moraes F, Ost L (2018) Exploring the Impact of Soft Errors on NoC-based Multiprocessor Systems. In Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5Google Scholar
  16. 16.
    Burns A, Davis RI (2017) A survey of research into mixed criticality systems. CSUR 50(6):82Google Scholar
  17. 17.
    Burns A et al (2014) A wormhole NoC protocol for mixed criticality systems. In Proc. IEEE Real-Time Systems Symposium, pp. 184–195Google Scholar
  18. 18.
    Certification Authorities Software Team (2014) CAST-32 position paper. Federal Aviation Administration / European Aviation Safety AgencyGoogle Scholar
  19. 19.
    Dally WJ, Towles B (2001) Route packets, not wires: on-chip interconnection networks. in Proc. 38th Design Automation Conference, pp. 684–689Google Scholar
  20. 20.
    de Dinechin B D, van Amstel D, Poulhiès M, Lager G (2014) Time-critical computing on a single-chip massively parallel processor. In Proc Conference on Design, Automation & Test in Europe (DATE), pp 97:1–97:6Google Scholar
  21. 21.
    Esposito S, Violante M et al (2017) A novel method for online detection of faults affecting execution-time in multicore-based systems. ACM Trans Embed Comput Syst 16(4):1–19CrossRefGoogle Scholar
  22. 22.
    Esposito S, Avramenko S, Violante M (2018) RTOS for mixed criticality applications deployed on NoC-based COTS MPSoC. In Proc. IEEE 19th Latin-American Test Symposium (LATS), pp. 1–6Google Scholar
  23. 23.
    Esposito S, Avramenko S, Violante M (2018) Efficient software-based partitioning for commercial-off-the-shelf NoC-based MPSoCs for mixed-criticality systems. In proc. IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), pp. 189–194Google Scholar
  24. 24.
    Fattah M et al (2014) Mixed-criticality run-time task mapping for noc-based many-core systems. In Proc. 22nd Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), pp. 458–465Google Scholar
  25. 25.
    Flich J, Duato J (2008) Logic-based distributed routing for NoCs. In proc. IEEE Comput Archit Lett 7(1):13–16CrossRefGoogle Scholar
  26. 26.
    Giannopoulou G et al (2013) Scheduling of mixed-criticality applications on resource-sharing multicore systems. In Proc. Int. Conf. Embed. Software, pp. 1–15Google Scholar
  27. 27.
    Giannopoulou G et al (2014) Mapping mixed-criticality applications on multi-core architectures. In Proc. Des. Autom. Test Eur. Conf. Exhib. (DATE), pp. 1–6Google Scholar
  28. 28.
    Giannopoulou G et al (2016) Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources. Real-Time Syst 52(4):399–449CrossRefGoogle Scholar
  29. 29.
    Goossens K, Dielissen J, Radulescu A (2007) Æthereal network on Chip: concepts, architectures, and implementations. IEEE Des. Test Comput. 22(5):414–421CrossRefGoogle Scholar
  30. 30.
    Hattendorf A, Raabe A, Knoll A (2012) Shared memory protection for spatial separation in multicore architectures. In Proc. 7th IEEE International Symposium on Industrial Embedded Systems (SIES), pp. 299–302Google Scholar
  31. 31.
    Hollstein T, Azad SP, Kogge T, Niazmand B (2015) Mixed-criticality NoC partitioning based on the NoCDepend dependability technique. In Proc. 10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip (ReCoSoC), pp. 1–8Google Scholar
  32. 32.
    Hughes WJ (2017) Assurance of Multicore Processors in Airborne Systems. DOT/FAA/TC-16/51. U.S. Department of Transportation Federal Aviation Administration. https://www.faa.gov/aircraft/air_cert/design_approvals/air_software/media/TC-16-51.pdf. Accessed 1 December 2018
  33. 33.
    Indrusiak LS, Harbin J, Burns A (2015) Average and worst-case latency improvements in mixed-criticality wormhole networks-on-Chip. In Proc. Euromicro Conference on Real-Time Systems, pp. 47–56Google Scholar
  34. 34.
    Marescaux T, Corporaal H (2007) Introducing the SuperGT network-on-chip. In Proc. Design Automation Conference, pp. 116–121Google Scholar
  35. 35.
    Nowotsch J et al (2014) Multi-core interference-sensitive WCET analysis leveraging runtime resource capacity enforcement. In Proc. Euromicro Conf. Real-Time Syst., pp. 109–118Google Scholar
  36. 36.
    Nowotsch J et al (2014) Monitoring and WCET analysis in COTS multi-core-SoC-based mixed-criticality systems. In Proc. Des. Autom. Test Eur. Conf. Exhib. (DATE), pp. 1–5Google Scholar
  37. 37.
    Paulitsch M, Driscoll K (2014) Industrial communication technology handbook. Capter 48 SAFEbus. CRC pressGoogle Scholar
  38. 38.
    Paulitsch M, Duarte O M, Karray H, Mueller K, Muench D, Nowotsch J (2015) Mixed-Criticality Embedded Systems -- A Balance Ensuring Partitioning and Performance. In Proc. Euromicro Conference on Digital System Design, pp. 453–461Google Scholar
  39. 39.
    Paulitsch M et al (2015) Mixed-criticality embedded systems – a balance ensuring partitioning and performance. In Proc. Euromicro Conference on Digital System Design (DSD), pp. 453–461Google Scholar
  40. 40.
    Pellizzoni R et al (2011) A predictable execution model for COTS-based embedded systems. In Proc. Real-Time Technol. Appl., pp. 269–279Google Scholar
  41. 41.
    Prisaznuk PJ (1992) Integrated modular avionics. In Proc. Aerosp. Electron. Conf., vol. 1, pp. 39–45Google Scholar
  42. 42.
    Prisaznuk PJ (2008) ARINC 653 role in Integrated Modular avionics (IMA). In Proc. IEEE Dig. Avionics Sys. ConfGoogle Scholar
  43. 43.
    Radack D, Tiedeman H G, Parkinson P (2018) Civil certification of multi-core processing Systems in Commercial Avionics. Rockwell Collins. https://www.rockwellcollins.com/-/media/files/unsecure/products/product-brochures/computing/processing-mission-computers/multi-core-certification-white-paper.pdf. Accessed 1 Dec 2018
  44. 44.
    Rajkumar RR, Lee I, Sha L, Stankovic J (2010) Cyber-physical systems: the next computing revolution. in Proc. 47th Design Automation Conference (DAC), pp. 731–736Google Scholar
  45. 45.
    Rushby J (1999) Partitioning in Avionics Architectures: Requirements, Mechanisms, and Assurance. NASA Langley Research Center, NASA CR-1999-209347Google Scholar
  46. 46.
    Schranzhofer A, Chen J-J, Thiele L (2009) Timing predictability on multi-processor systems with shared resources. In Proc. Embed. Syst. Week-Workshop Reconciling Perform. with Predict., p. 89Google Scholar
  47. 47.
    Triviño F, Sánchez J, Alfaro F, Flich J (2012) Network-on-Chip virtualization in Chip- multiprocessor systems. JSA 58(3–4):126–139Google Scholar
  48. 48.
    Vestal S (2007) Preemptive scheduling of multi-criticality systems with varying degrees of execution time assurance. In Proc. Real-Time Syst. Symp, pp. 239–243Google Scholar
  49. 49.
    Watkins CB, Walter R (2007) Transitioning from federated avionics architectures to integrated modular Avionics. in Proc. IEEE 26th Digital Avionics Systems Conference, pp. 2.A.1-1-2.A.1-10Google Scholar
  50. 50.
    Xiong Q, Wu F et al (2017) Extending real-time analysis for wormhole NoCs. IEEE Trans Comput 66(9):1532–1546MathSciNetCrossRefzbMATHGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Politecnico di TorinoTorinoItaly

Personalised recommendations

Cite article

Buy options