Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy

  • Paulo R. C. VillaEmail author
  • Rodrigo Travessini
  • Roger C. Goerl
  • Fabian L. Vargas
  • Eduardo A. Bezerra


Embedded soft-core processors are becoming the usual solution to deal with network and data communications inside FPGAs. However, when developing space-based applications, the designer must consider the effects of ionizing radiation such as Total Ionizing Dose (TID) and Single-Event Effect (SEE). The majority of techniques for mitigation of Single-Event Upsets (SEUs) on FPGAs are based on hardware spatial-redundancy. This work presents a fault-tolerance technique, based on the concept of temporal redundancy, with checkpoints and recovery for soft-core processors. The proposed modified architecture is aimed at embedded systems for space applications based on FPGAs. Our experimental results show that the Checkpoint Recovery technique is a valid alternative to traditional spatial-redundancy, especially when considering limited logic area and power budget present on a satellite. The results present levels of reliability comparable to those of the more conventional fault-tolerance techniques. Additionally, the proposed approach does not require modifications of the software source code or compiler.


Fault-tolerance Checkpoint recovery Soft-core processors FPGAs Single-event upsets 



This work has been partly funded by the Brazilian National Council for Scientific and Technological Development (CNPq) and Instituto Federal do Rio Grande do Sul (IFRS).


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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Federal Institute of Rio Grande do SulVeranópolisBrazil
  2. 2.Electrical Engineering DepartmentFederal University of Santa CatarinaFlorianópolisBrazil
  3. 3.Electrical Engineering DepartmentCatholic University - PUCRSPorto AlegreBrazil
  4. 4.Electrical Engineering Department, UFSC, Brazil and LIRMMUniversité de MontpellierMontpellierFrance

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