Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies

  • Amit Karel
  • Florence AzaïsEmail author
  • Mariane Comte
  • Jean-Marc Gallière
  • Michel Renovell


This paper deals with the analysis of the impact of process variations on the detection of resistive short defects, in the context of a logic-based test. Two types of short defects are considered for our investigation, i.e. resistive short to either ground terminal (GND) or power supply terminal (VDD). For both defect types, simple analytical models are proposed that permit to evaluate the robust detectability range in presence of process variations. These models rely on a pre-characterization of the gate library through Monte-Carlo simulation and permit to evaluate the detectability range of a given defect without performing any fault simulation. These models are applied to perform a comparative analysis of 28 nm Bulk and FDSOI (Fully Depleted Silicon-On-Insulator) technologies, considering both regular-VT and low-VT devices. The influence of operating conditions on defect detectability range is also investigated.


Resistive short defects Process variations Modelling Logic-based test Defect detectability Bulk FDSOI 



  1. 1.
    Nowak EJ et al (2004) Turning silicon on its edge double gate CMOS/FinFET technology. IEEE Circuits and Devices Magazine 20(1):20–31MathSciNetCrossRefGoogle Scholar
  2. 2.
    Iwai H (2008) CMOS technology after reaching the scale limit Proc 8th International Workshop on Junction Technology (IWJT), pp1–2Google Scholar
  3. 3.
    Magarshack P et al (2013) UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency Proc Design Automation & Test in Europe (DATE), 952–957Google Scholar
  4. 4.
    Mäkipää J et al (2013) FDSOI versus BULK CMOS at 28nm node which technology for ultra-low power design?, Proc IEEE Int’l Symp on Circuits and Systems (ISCAS), pp. 554–557Google Scholar
  5. 5.
    Makovejev S et al (2015) Self-heating in 28 nm bulk and FDSOI," EUROSOI-ULIS: proc. joint international EUROSOI workshop and Int’l conference on ultimate integration on Silicon, pp. 41–44Google Scholar
  6. 6.
    Renovell M, Hue P, Bertrand Y (1995) The concept of resistance interval: a new parametric model for realistic resistive bridging fault. Proc VLSI Test Symp (VTS), pp184–189Google Scholar
  7. 7.
    Polian, I. et al (2005) Resistive bridge fault model evolution from conventional to ultra-deep submicron. Proc. IEEE VLSI Test Symposium (VTS), pp. 343–348, 2005Google Scholar
  8. 8.
    Rossello JL, de Benito C, Bota SA, Segura J, (2007)Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. Proc Design, Automation & Test in Europe (DATE), p. 6Google Scholar
  9. 9.
    Engelke P et al (2004) The pros and cons of very-low-voltage testing: an analysis based on resistive bridging faults. Proc VLSI Test Symp (VTS), pp. 171–178Google Scholar
  10. 10.
    Engelke P et al (2008) On detection of resistive bridging defects by low-temperature and low-voltage testing. IEEE Trans on Computer-Aided Design, vol. 27, no. 2, pp. 327–338Google Scholar
  11. 11.
    Villacorta H, Champac V, Bota S, Segura J (2012) Resistive bridging defect detection enhancement under parameter variations combining low VDD and body bias in a delay based test. Microelectron Reliab 52(11):2799–2804Google Scholar
  12. 12.
    Ingelsson, B. et al., "Process variation-aware test for resistive bridges," in IEEE Trans Computer-Aided Design, vol. 28, no. 8, pp. 1269–1274, 2009Google Scholar
  13. 13.
    Zhong S et al (2013) Impact of PVT variation on delay test of resistive open and resistive bridge defects Proc Int’l Symp on Defect and Fault Tolerance (DFTS), pp. 230–235Google Scholar
  14. 14.
    Karel A et al (2016) Comparative study of bulk, FDSOI and FinFET technologies in presence of a resistive short defect. Proc Latin-American Test Symp (LATS), pp. 129–134Google Scholar
  15. 15.
    Karel A et al (2016) Impact of VT and body- biasing on resistive short detection in 28nm UTBB FDSOI - LVT and RVT configuration. Proc IEEE CS Annual Symp on VLSI (ISVLSI), pp. 164–169Google Scholar
  16. 16.
    Karel A et al (2018) Impact of process variations on the detectability of resistive short defects: comparative analysis between 28nm bulk and FDSOI technologies. Proc Latin-American Test Symp (LATS), p5Google Scholar
  17. 17.
    Skotnicki T et al (2008) Innovative materials, devices, and CMOS Technologies for low-Power Mobile Multimedia. IEEE Trans Electron Devices 55(1):96–130CrossRefGoogle Scholar
  18. 18.
    Takayasu S et al (2006) Fully-depleted SOI CMOS circuits and technology for ultra-low power application. Springer,Google Scholar
  19. 19.
    Pelloux-Prayer B et al (2013) Performance analysis of multi-VT design solutions in 28nm FD-SOI technology. Proc. SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 1–2Google Scholar
  20. 20.
    Karel A et al (2017) Influence of body- biasing, supply voltage and temperature on the detection of resistive short defects in FDSOI technology. IEEE Trans Nanotechnol 16(3):417–430CrossRefGoogle Scholar
  21. 21.
    Stuart A, Ord K (2010) Kendall's Advanced Theory of Statistics, vol 1, 6th edn. John Wiley & Sons, New YorkzbMATHGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  • Amit Karel
    • 1
  • Florence Azaïs
    • 1
    Email author
  • Mariane Comte
    • 1
  • Jean-Marc Gallière
    • 1
  • Michel Renovell
    • 1
  1. 1.LIRMMCNRS / Université MontpellierMontpellier Cedex 5France

Personalised recommendations