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Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies

  • Amit Karel
  • Florence AzaïsEmail author
  • Mariane Comte
  • Jean-Marc Gallière
  • Michel Renovell
Article
  • 3 Downloads

Abstract

This paper deals with the analysis of the impact of process variations on the detection of resistive short defects, in the context of a logic-based test. Two types of short defects are considered for our investigation, i.e. resistive short to either ground terminal (GND) or power supply terminal (VDD). For both defect types, simple analytical models are proposed that permit to evaluate the robust detectability range in presence of process variations. These models rely on a pre-characterization of the gate library through Monte-Carlo simulation and permit to evaluate the detectability range of a given defect without performing any fault simulation. These models are applied to perform a comparative analysis of 28 nm Bulk and FDSOI (Fully Depleted Silicon-On-Insulator) technologies, considering both regular-VT and low-VT devices. The influence of operating conditions on defect detectability range is also investigated.

Keywords

Resistive short defects Process variations Modelling Logic-based test Defect detectability Bulk FDSOI 

Notes

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  • Amit Karel
    • 1
  • Florence Azaïs
    • 1
    Email author
  • Mariane Comte
    • 1
  • Jean-Marc Gallière
    • 1
  • Michel Renovell
    • 1
  1. 1.LIRMMCNRS / Université MontpellierMontpellier Cedex 5France

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