Impact of Negative Bias Temperature Instability on Gate-All-Around Flip-Flops

  • Shiva Taghipour
  • Rahebeh Niaraki AsliEmail author


Negative bias temperature instability is an important reliability issue for FinFET and gate-all-around nanowire FETs at next-generation technology nodes which leads to circuit failure during the life time of the device. This paper compares the performance parameters of widely used FinFET and gate-all-around flip-flop structures through HSPICE at VDD = 0.7 V to show the power and PDP superiority of gate-all-around flip-flops. Furthermore, the NBTI degradation analysis of FinFET and gate-all-around flip-flops is conducted by MOSRA simulation. The reliability analyses demonstrate that the performance degradation of gate-all-around structures within the range of less than 4.3% is smaller than FinFET flip-flops. The simulation results of this paper also help designers to choose a high performance or low power flip-flop design according to their works. In addition, this paper introduces reliable flip-flop circuits for long-term usage in both FinFET and gate-all-around technologies. Temperature and VDD variation effects on aging analysis approve the efficiency of gate-all-around flip-flops.


Gate-all-around FinFET Flip-flop NBTI Reliability 



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© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Engineering FacultyUniversity of GuilanRashtIran

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