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Journal of Electronic Testing

, Volume 34, Issue 5, pp 571–586 | Cite as

Impact of Aging on the Reliability of Delay PUFs

  • Naghmeh KarimiEmail author
  • Jean-Luc Danger
  • Sylvain Guilley
Article
  • 153 Downloads

Abstract

Physically Unclonable Functions (PUFs) are mainly used for generating unique keys to identify electronic devices. These entities mainly benefit from the process variations occurring during the device manufacturing. To be able to use PUFs to identify electronic devices or to utilize them in cryptographic applications, the reliability of PUFs needs to be assured under a wide variety of environmental conditions and aging mechanisms, including the switching activity of the PUFs’ internal signals. In practice, it is important to evaluate aging effects as early as possible, preferentially at design time. In this paper, we evaluate the impact of aging on two types of delay-PUFs (arbiter-PUFs and loop-PUFs) with different switching activities. This work takes advantage of both simulation tool and silicon tests on a 65nm ASIC implementation. To expedite the simulation process and get rid of conducting simulations of multiple delay-element PUFs, we propose an extrapolation method to evaluate the effect of BTI (Bias Temperature-Instability) and HCI (Hot Carrier Injection) aging under different switching activities on PUFs with multiple delay elements using the aging effects on single delay-element PUFs. The results show that switching activity (expressed in terms of transitions/time) has a limited impact on delay chains of considered delay-PUFs, while it has a greater impact on the arbiter (RS latch) of the arbiter-PUF. The simulation results show that the aging-related Bit Error Rate in an arbiter-PUF with high switching activity can be 11 times worse than the Bit Error Rate in the same PUF when there is no activity in 20 months.

Keywords

Hardware security Physically Unclonable Functions (PUFs) Delay-PUFs Device aging Reliability 

Notes

Acknowledgments

This work was partly supported by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIT) (No.2016-0-00399, Study on secure key hiding technology for IoT devices [KeyHAS Project]). It was also partly supported by a Faculty Fellowship Award from University of Maryland Baltimore County.

References

  1. 1.
    Alam MA, Kufluoglu H, Varghese D, Mahapatra S (2007) A comprehensive model for PMOS NBTI degradation: recent progress. Microelectron Reliab 47(6):853–862CrossRefGoogle Scholar
  2. 2.
    Bhargava M, Mai K (2014) An efficient reliable PUF-based cryptographic key generator in 65nm CMOS. In: Design, automation & test in Europe (DATE), pp 70:1–70:6Google Scholar
  3. 3.
    Cao Y, Zhang L, Chang C, Chen S (2015) A low-power hybrid RO PUF with improved thermal stability for lightweight applications. IEEE Trans CAD Integrated Circ Syst 34(7):1143–1147CrossRefGoogle Scholar
  4. 4.
    Cha S, Chen C-C, Liu T, Milor LS (2014) Extraction of threshold voltage degradation modeling due to negative bias temperature instability in circuits with I/O measurements. In: VLSI test symposium (VTS), pp 1–6Google Scholar
  5. 5.
    Cherif Z, Danger J-L, Guilley S, Bossuet L (2012) An easy-to-design PUF based on a single oscillator: the Loop PUF in DSDGoogle Scholar
  6. 6.
    Cherif Z, Danger J-L, Lozac’h F, Mathieu Y, Bossuet L (2013) Evaluation of delay PUFs on cmos 65 nm technology: ASIC vs FPGA. In: International workshop on hardware and architectural support for security and privacy (HASP), pp 4:1–4:8Google Scholar
  7. 7.
    Ching SP, Ping CT, Sun YH (2008) Studies of the critical LDD area for HCI improvement. In: International conference on semiconductor electronics, pp 622–625Google Scholar
  8. 8.
    Crupi F, Pace C, Cocorullo G, Groeseneken G, Aoulaiche M, Houssa M (2005) Positive bias temperature instability in nMOSFETs with ultra-thin hf-silicate gate dielectrics. Microelectron Eng 80:130–133CrossRefGoogle Scholar
  9. 9.
    Gassend B, Clarke DE, van Dijk M, Devadas S (2002) Silicon physical random functions. In: ACM conference on computer and communications security, CCS 2002, pp 148–160Google Scholar
  10. 10.
    Gerrer L, Ding J, Amoroso SM, Adamu-Lema F, Hussin R, Reid D, Millar C, Asenov A (2014) Modelling RTN and BTI in nanoscale MOSFETs from device to circuit: a review. Microelectron Reliab 54 (4):682–697CrossRefGoogle Scholar
  11. 11.
    Guajardo J, Kumar SS, Schrijen G-J, Tuyls P (2007) FPGA intrinsic PUFs and their use for IP protection. In: Cryptographic hardware and embedded systems (CHES), pp 63–80Google Scholar
  12. 12.
    Holcomb DE, Burleson WP, Fu K (2009) Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Trans Comput 58(9):1198–1210MathSciNetCrossRefGoogle Scholar
  13. 13.
    Hori Y, Yoshida T, Katashita T, Satoh A (2010) Quantitative and statistical performance evaluation of arbiter physical unclonable functions on FPGAs. In: International conference on reconfigurable computing and FPGAs, pp 298–303Google Scholar
  14. 14.
    Hosey A, Rahman MT, Xiao K, Forte D, Tehranipoor M (2014) Advanced analysis of cell stability for reliable SRAM PUFs. In: Asian test symposium (ATS), pp 348–353Google Scholar
  15. 15.
    JEDEC (2011) JEP122G: Failure mechanisms and models for semiconductor devices, http://www.jedec.org/standards-documents/docs/jep-122e
  16. 16.
    Karimi N, Danger J-L, Guilley S, Lozach F (2016) Predictive aging of reliability of two delay PUFs. In: Security, privacy, and applied cryptography engineering (SPACE), pp 213–232CrossRefGoogle Scholar
  17. 17.
    Karimi N, Slimani J-LDM, Guilley S (2017) Impact of the switching activity on the aging of delay-PUFs. In: European Test Symp. (ETS)Google Scholar
  18. 18.
    Karimi N, Guilley S, Danger J- L (2018) Impact of aging on template attacks. In: Proceedings of the ACM great lakes symposium on VLSI (GlSVLSI), pp 455–458Google Scholar
  19. 19.
    Karimi N, Danger J-L, Guilley S (2018) On the effect of aging in detecting hardware trojan horses with template analysis. In: Proceedings of the international symposium on on-line testing and robust system design (IOLTS)Google Scholar
  20. 20.
    Kim KK (2015) On-chip delay degradation measurement for aging compensation. Indian J Sci Technol 8:8Google Scholar
  21. 21.
    Kirkpatrick MS, Bertino E (2010) Software techniques to combat drift in PUF-based authentication systems. In: Workshop on secure component and system identification (SECSI), p 9Google Scholar
  22. 22.
    Krishnan AT, Chancellor C, Chakravarthi S, Nicollian PE, Reddy V, Varghese A, Khamankar R, Krishnan S (2005) Material dependence of hydrogen diffusion: implications for NBTI degradation. In: International electron devices meeting (IEDM), pp 688–691Google Scholar
  23. 23.
    Kufluoglu H, Alam MA (2007) A generalized reaction-diffusion model with explicit h-h2 dynamics for negative-bias temperature-instability (NBTI) degradation. IEEE Trans Electron Dev 54(5):1101–1107CrossRefGoogle Scholar
  24. 24.
    Lu Y, Shang L, Zhou H, Zhu H, Yang F, Zeng X (2009) Statistical reliability analysis under process variation and aging effects. In: Design automation conference (DAC), pp 514–519Google Scholar
  25. 25.
    Maes R, van der Leest V (2014) Countering the effects of silicon aging on SRAM PUFs. In: International symposium hardware-oriented security and trust (HOST), pp 148–153Google Scholar
  26. 26.
    Mahapatra S, Saha D, Varghese D, Kumar P (2006) On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress. IEEE Trans Electron Dev 53(7):1583–1592CrossRefGoogle Scholar
  27. 27.
    Maiti A, Schaumont P (Sep 2014) The impact of aging on a physical unclonable function. IEEE Trans Very Large Scale Integrated Syst (TVLSI) 22(9):1854–1864CrossRefGoogle Scholar
  28. 28.
    Mispan MS, Halak B, Zwolinski M (2016) NBTI aging evaluation of PUF-based differential architectures. In: International symposium on on-line testing and robust system design (IOLTS), pp 103–108Google Scholar
  29. 29.
    Mizan E (2008) Efficient fault tolerance for pipelined structures and its application to superscalar and dataflow machines. Ph.D. thesis, Electrical and Computer Engineering Dept. University of Texas At AustinGoogle Scholar
  30. 30.
    Morozov S, Maiti A, Schaumont P (2010) An analysis of delay based PUF implementations on FPGA. In: Reconfigurable computing: architectures, tools and applications (ARC), pp 382–387Google Scholar
  31. 31.
    Nangate 45nm open cell library, http://www.nangate.com. (Last Accessed 1 May 2016)
  32. 32.
    Nunes C, Butzen PF, Reis AI, Ribas RP (2013) BTI, HCI and TDDB aging impact in flip-flops. Microelectron Reliab 53(6-11):1355–1359CrossRefGoogle Scholar
  33. 33.
    Oboril F, Tahoori MB (2012) Extratime: modeling and analysis of wearout due to transistor aging at microarchitecture-level. In: Dependable systems and networks (DSN), pp 1–12Google Scholar
  34. 34.
    Pelgrom MJ, Duinmaijer AC, Welbers AP (1989) Matching properties of MOS transistors. IEEE J Solid State Circuits 24(5):1433–1439CrossRefGoogle Scholar
  35. 35.
    Rahman MT, Forte D, Fahrny J, Tehranipoor M (2014) ARO-PUF: an aging-resistant ring oscillator PUF design. In: Design, automation test in Europe conference (DATE), pp 1–6Google Scholar
  36. 36.
    Rahman MT, Rahman F, Forte D, Tehranipoor M (July 2016) An aging-resistant RO-PUF for reliable key generation. IEEE Trans Emerg Topics Comput 4(3):335–348Google Scholar
  37. 37.
    Rioul O, Solé P, Guilley S, Danger J-L (2016) On the entropy of physically unclonable functions. In: IEEE international symposium on information theory (ISIT). BarcelonaGoogle Scholar
  38. 38.
    Rodriguez R, Stathis J, Linder B (2003) Modeling and experimental verification of the effect of gate oxide breakdown on CMOS inverters. In: IEEE international reliability physics symposium, pp 11–16Google Scholar
  39. 39.
    Rukhin A, et al. (2001) A statistical test suite for random and pseudorandom number generators for cryptographic applications. National Institute of Standards and Technology (NIST)Google Scholar
  40. 40.
    Schroder DK (2007) Negative bias temperature instability: what do we understand? Microelectron Reliab 47 (6):841–852CrossRefGoogle Scholar
  41. 41.
    Suh GE, Devadas S (2007) Physical unclonable functions for device authentication and secret key generation. In: Design automation conference (DAC), pp 9–14Google Scholar
  42. 42.
    Sutaria KB, Velamala JB, Ramkumar A, Cao Y (2015) Compact modeling of BTI for circuit reliability analysis. In: Circuit design for reliability, pp 93–119Google Scholar
  43. 43.
    Synopsys (2016) HSPICE user guide: basic simulation and analysisGoogle Scholar
  44. 44.
    Tiwari A, Torrellas J (2008) Facelift: hiding and slowing down aging in multicores. In: International symposium on microarchitecture, pp 129–140Google Scholar
  45. 45.
    Wang W, Yang S, Bhardwaj S, Vrudhula S, Liu F, Cao Y (2010) The impact of NBTI effect on combinational circuit: modeling, simulation, and analysis. IEEE Trans Very Large Scale Integr Syst 18(2):173–183CrossRefGoogle Scholar
  46. 46.
    Xiao K, Rahman MT, Forte D, Huang Y, Su M, Tehranipoor M (2014) Bit selection algorithm suitable for high-volume production of SRAM-PUF. In: International symposium on hardware-oriented security and trust (HOST), pp 101–106Google Scholar
  47. 47.
    Yilmaz M, Chakrabarty K, Tehranipoor M (2008) Test-pattern grading and pattern selection for small-delay defects. In: VTS, pp 233–239Google Scholar
  48. 48.
    Zafar S, Kim Y, Narayanan V, Cabral C, Paruchuri V, Doris B, Stathis J, Callegari A, Chudzik M (2006) A comparative study of NBTI and PBTI (charge trapping) in SiO2/HfO2 stacks with FUSI, TiN, Re gates. In: Symposium on VLSI technology, pp 23–25Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.CSEE DepartmentUniversity of Maryland Baltimore CountyBaltimoreUSA
  2. 2.Institut Mines-TelecomTelecom ParisTechParisFrance
  3. 3.Secure-IC S.A.S.Cesson-SévignéFrance
  4. 4.Ecole Normale Supérieure (ENS)Département d’InformatiqueParisFrance

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