Journal of Electronic Testing

, Volume 34, Issue 3, pp 321–335 | Cite as

A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters

  • Ahcène Bounceur
  • Samia Djemai
  • Belkacem Brahmi
  • Mohand Ouamer Bibi
  • Reinhardt Euler


Specifications of Radio Frequency (RF) analog integrated circuits have increased strictly as their applications tend to be more complicated and high test cost demanding. This makes them very expensive due to an increased test time and to the use of sophisticated test equipment. Alternative test measures, extracted by means of Built-In Self Test (BIST) techniques, are useful approaches to replace standard specification-based tests. One way to evaluate the efficiency of the CUT measures at the design stage is by estimating the Test Escapes (T E ) and the Yield Loss (Y L ) at ppm level. Unfortunately, an important number of Monte Carlo simulations must be run in order to guarantee their accuracy. For certain types of circuits, this requires many months or even years to generate millions of circuits. To overcome this limitation, we present in this paper a new technique where a small number of simulations is sufficient to reach an important precision. This method is based on a classification using machine learning methods, such as SVM and Neural Networks based classifiers to determine pass/fail regions. The proposed approach requires a few number of simulations only to determine the region separating the process parameters generating good and faulty, or pass and fail circuits. Then only this region is needed to estimate the test metrics without running any additional simulation. The proposed methodology is illustrated for the evaluation of a filter BIST technique.


Analog/RF test SVM classification Neural network classification BIST evaluation 


  1. 1.
    Akbay SS, Torres JL, Rumer JM, Chatterjee A, Amtsfield J (2006) Alternate test of RF front ends with IP constraints Frequency domain test generation and validation. In: IEEE international test conference (ITC’06), pp 1–10Google Scholar
  2. 2.
    Akkouche N, Mir S, Simeu E, Slamani M (2012) Analog/RF test ordering in the early stages of production testing. In: IEEE 30th VLSI test symposium (VTS), pp 25–30Google Scholar
  3. 3.
    Aminian F, Aminian M, Collins HW Jr (2002) Analog fault diagnosis of actual circuits using neural networks. IEEE Trans Instrum Meas 51(3):544–550CrossRefGoogle Scholar
  4. 4.
    Arabi K, Kaminska B (1999) Oscillation-test methodology for low-cost testing of active analog filters. IEEE Trans Instrum Meas 48(4):798–806CrossRefGoogle Scholar
  5. 5.
    Beznia K (2013) Méthodes statistiques pour l’évaluation des techniques de test de circuits analogiques sous variations paramétriques multiples Thesis reportGoogle Scholar
  6. 6.
    Beznia K, Bounceur A, Euler R, Mir S (2015) A tool for analog/RF BIST evaluation using statistical models of circuit parameters. ACM Trans Des Autom Electron Syst 20(2):31:1-31:22CrossRefGoogle Scholar
  7. 7.
    Beznia K, Bounceur A, Mir S, Euler R (2012) Accurate estimation of analog test metrics with extreme circuits. In: IEEE international conference on electronics, circuits and systems (ICECS’12)Google Scholar
  8. 8.
    Beznia K, Bounceur A, Mir S, Euler R (2013) Statistical modelling of analog circuits for test metrics computation. In: 8th international conference on design & technology of integrated systems in Nanoscale Era (DTIS) 25–29Google Scholar
  9. 9.
    Biswas S, Blanton RD (2006) Statistical test compaction using binary decision trees. IEEE Des Test Comput 23(6):452–462CrossRefGoogle Scholar
  10. 10.
    Biswas S, Li P, Blanton RD, Pileggi LT (2005) Specification test compaction for analog circuits and MEMS The conference on Design, Automation and Test in Europe-Volume 1, 164– 169Google Scholar
  11. 11.
    Bounceur A, Brahmi B, Beznia K, Euler R (2014) Accurate analog/RF BIST evaluation based on SVM classification of the process parameters. In: The 9th IEEE international design and test symposium (IDT), pp 55–60Google Scholar
  12. 12.
    Bounceur A, Mir S, Simeu E, Rolíndez L (2007) Estimation of test metrics for the optimization of analog circuit testing. J Electron Test Theory Appl 23(6):471–484CrossRefGoogle Scholar
  13. 13.
    Bounceur A, Mir S, Stratigopoulos H-G (2011) Estimation of analog parametric test metrics using copulas. IEEE Trans Comput Aided Des Integr Circuits Syst 30(09):1400–1410CrossRefGoogle Scholar
  14. 14.
    Brahmi B, Bibi MO (2010) Dual support method for solving convex quadratic programs. Optimization 59:851–872MathSciNetCrossRefzbMATHGoogle Scholar
  15. 15.
    Brockman JB, Director SW (1989) Predictive subset testing: Optimizing IC parametric performance testing for quality, cost, and yield. IEEE Trans Semicond Manuf 2(3):104–113CrossRefGoogle Scholar
  16. 16.
    Cai S, Yuan H, Lv J, Cui Y (2013) Application of IWO-SVM approach in fault diagnosis of analog circuits. In: 25th Chinese control and decision conference (CCDC), pp 4786–4791Google Scholar
  17. 17.
    Chao C-Y, Lin H-J, Miler L (1997) Optimal testing of VLSI analog circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 16(1):58–77CrossRefGoogle Scholar
  18. 18.
    Djemai S, Brahmi B, Bibi MO (2014) Méthode primale-duale pour l’apprentissage des SVM. In: COSI’2014, pp 189–197Google Scholar
  19. 19.
    Djemai S, Brahmi B, Bibi MO (2016) A primal-dual method for training SVM, 211, 34–40Google Scholar
  20. 20.
    Dubois M, Stratigopoulos H-G, Mir S (2009) Hierarchical parametric test metrics estimation: A \({\Sigma } {\Delta }\) converter BIST case study. In: IEEE international conference on computer design (ICCD), pp 78–83Google Scholar
  21. 21.
    Gabasov R, Kirillova FM, Raketsky VM, Kostyukova OI (1987) Constructive methods of optimization. Volume 4 : Convex Problems, Minsk University PressGoogle Scholar
  22. 22.
    Gómez-Pau A, Balado L, Figueras J (2013) MS test based on specification validation using octrees in the measure space. In: 18th IEEE European test symposium (ETS), pp 1–6Google Scholar
  23. 23.
    Grzechca D, Golonek T, Rutkowski J (2006) Analog fault AC dictionary creation-the fuzzy set approach. In: IEEE international symposium on circuits and systems (ISCASGoogle Scholar
  24. 24.
    Gu X-F, Liu L, Li J-P, Huang Y-Y, Lin J (2008) Data classification based on artificial neural networks. In: International conference on apperceiving computing and intelligence analysis, pp 223–226Google Scholar
  25. 25.
    Hagan MT, Demuth HB, Beale MH et al. (1996) Neural network design. Pws Pub. BostonGoogle Scholar
  26. 26.
    Hsu C-W, Chang C-C, Lin C-J et al. (2003) A practical guide to support vector classificationGoogle Scholar
  27. 27.
    Huang J, Hu X, Yang F (2011) Support vector machine with genetic algorithm for machinery fault diagnosis of high voltage circuit breaker. Measurement 44(6):1018–1027CrossRefGoogle Scholar
  28. 28.
    Huertas G, Vázquez D, Peralías EJ, Rueda A, Huertas JL (2002) Practical oscillation-based test of integrated filters. IEEE Des Test Comput 19(6):64–72CrossRefGoogle Scholar
  29. 29.
    Lin PM, Elcherif YS (1985) Analog circuits fault dictionary: New approaches and implementation. Int J Circuit Theory Appl 13(2):149–172CrossRefGoogle Scholar
  30. 30.
    Long B, Tian S, Wang H (2012) Diagnostics of filtered analog circuits with tolerance based on LS-SVM using frequency features. J Electron Test 28(3):291–300CrossRefGoogle Scholar
  31. 31.
    Milor L, Sangiovanni-Vincentelli AL (1994) Minimizing production test time to detect faults in analog circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 13(6):796–813CrossRefGoogle Scholar
  32. 32.
    Pulka A (2007) A heuristic fault dictionary reduction methodology. In: 14th IEEE international conference on electronics circuits and systemsGoogle Scholar
  33. 33.
    Radjef S, Bibi MO (2012) An effective generalization of the direct support method in quadratic convex programming. Appl Math Sci 6(31):1525–1540MathSciNetzbMATHGoogle Scholar
  34. 34.
    Singhee A, Rutenbar RA (2009) Statistical Blockade: Very fast statistical simulation and modeling of rare circuit events and its application to memory design. IEEE Trans Comput Aided Des Integr Circuits Syst 28(8):1176–1189CrossRefGoogle Scholar
  35. 35.
    Starzyk J, Liu D, Liu Z-H, Nelson DE, Rutkowski JO et al. (2004) Entropy-based optimum test points selection for analog fault dictionary techniques. IEEE Trans Instrum Meas 53(3):754– 761CrossRefGoogle Scholar
  36. 36.
    Stratigopoulos H (2012) Test metrics model for analog test development. IEEE Trans Comput Aided Des Integr Circuits Syst 31(07):1116–1128CrossRefGoogle Scholar
  37. 37.
    Stratigopoulos H, Mir S (2010) Analog test metrics estimates with PPM accuracy. In: IEEE/ACM international conference on computer-aided design (ICCAD), pp 241–247Google Scholar
  38. 38.
    Stratigopoulos H-G, Mir S, Bounceur A (2009) Evaluation of analog/RF test measurements at the design stage. IEEE Trans Comput Aided Des Integr Circuits Syst 28(4):582–590CrossRefGoogle Scholar
  39. 39.
    Stratigopoulos HG, Drineas P, Slamani M, Makris Y (2010) RF specification test compaction using learning machines. IEEE Trans Very Large Scale Integr VLSI Syst 18(6):998– 1002CrossRefGoogle Scholar
  40. 40.
    Sunter S (2006) Mixed-signal testing and DFT, advances in electronic testing. In: D. Gizopoulos (Ed). Springer. p 301–336Google Scholar
  41. 41.
    Vladimir NV (1995) The Nature of Statistical Learning Theory. Springer New York, Inc., New YorkzbMATHGoogle Scholar
  42. 42.
    Vasan ASS, Long B, Pecht M (2014) Experimental validation of LS-SVM based fault identification in analog circuits using frequency features Engineering Asset Management. Springer, New York, pp 629–641Google Scholar
  43. 43.
    Voorakaranam R, Akbay SS, Bhattacharya S, Cherubal S, Chatterjee A (2007) Signature testing of analog and RF circuits Algorithms and methodology. IEEE Trans Circuits Syst Regul Pap 54(5):1018–1031CrossRefGoogle Scholar
  44. 44.
    Yuan L, He Y, Huang J, Sun Y (2010) A new neural-network-based fault diagnosis approach for analog circuits by using kurtosis and entropy as a preprocessor. IEEE Trans Instrum Meas 59(3):586–595CrossRefGoogle Scholar

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© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Lab-STICC LaboratoryUniversity of BrestBrestFrance
  2. 2.LaMOS Research Unit, Department of MathematicsUniversity of JijelJijelAlgeria
  3. 3.LaMOS Research Unit, Department of Operational ResearchUniversity of BejaiaBejaiaAlgeria

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