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Journal of Electronic Testing

, Volume 32, Issue 3, pp 273–289 | Cite as

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

  • Maksim Jenihhin
  • Giovanni Squillero
  • Thiago Santos Copetti
  • Valentin Tihhomirov
  • Sergei Kostin
  • Marco Gaudesi
  • Fabian Vargas
  • Jaan Raik
  • Matteo Sonza Reorda
  • Leticia Bolzani Poehls
  • Raimund Ubar
  • Guilherme Cardoso Medeiros
Article

Abstract

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics.

Keywords

Hardware rejuvenation Aging NBTI Critical path identification Logic circuit Evolutionary computation MicroGP zamiaCAD 

Notes

Acknowledgments

This work has been supported in part by projects EU FP7 CP BASTION,  H2020 RIA IMMORTAL and H2020 TWINN TUTORIAL, by CNPq (Science and Technology Foundation, Brazil) under contract n. 303701/2011-0 (PQ) and FAPERGS/CAPES under contract n. 014/2012.

Authors would like to acknowledge Dr. Christoph Werner, from TU Munich, Germany for valuable comments regarding the proposed approach.

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Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  • Maksim Jenihhin
    • 1
  • Giovanni Squillero
    • 2
  • Thiago Santos Copetti
    • 3
  • Valentin Tihhomirov
    • 1
  • Sergei Kostin
    • 1
  • Marco Gaudesi
    • 2
  • Fabian Vargas
    • 3
  • Jaan Raik
    • 1
  • Matteo Sonza Reorda
    • 2
  • Leticia Bolzani Poehls
    • 3
  • Raimund Ubar
    • 1
  • Guilherme Cardoso Medeiros
    • 3
  1. 1.Department of Computer EngineeringTallinn University of TechnologyTallinnEstonia
  2. 2.Politecnico di Torino, Department of Control and Computer EngineeringTorinoItaly
  3. 3.Catholic University – PUCRSPorto AlegreBrazil

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