Journal of Electronic Testing

, Volume 29, Issue 2, pp 127–141

On the Simulation of HCI-Induced Variations of IC Timings at High Level

  • Olivier Heron
  • Clement Bertolini
  • Chiara Sandionigi
  • Nicolas Ventroux
  • Francois Marc
Article

DOI: 10.1007/s10836-013-5368-x

Cite this article as:
Heron, O., Bertolini, C., Sandionigi, C. et al. J Electron Test (2013) 29: 127. doi:10.1007/s10836-013-5368-x

Abstract

Die shrinking combined with the non-ideal scaling of voltage increases the probability of MOS transistors to encounter HCI. This mechanism causes timing degradation and possibly failures in ICs. The evaluation of timing degradation early in the design flow becomes a must-have to ensure the expected time-to-market and IC lifetime. In this paper, we propose a framework for simulating and analyzing the HCI-induced timing variations at high abstraction level. We first present a bottom-up approach to move information about timing degradation up to the higher abstraction layers. Then, we describe a simulation framework for analyzing the HCI-induced timing variations, and we evaluate its performance and accuracy. Finally, by considering a sample processor, we analyze the impact of the instruction set architecture on slack times and critical paths.

Keywords

Hot carrier injection Timing degradation 

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Olivier Heron
    • 1
  • Clement Bertolini
    • 1
  • Chiara Sandionigi
    • 1
  • Nicolas Ventroux
    • 1
  • Francois Marc
    • 2
  1. 1.CEA, LIST, Embedded Computing Laboratory, PC172Gif-sur-Yvette CedexFrance
  2. 2.Universite Bordeaux 1, ENSEIRB, UMR 5218 CNRSTalence CedexFrance

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