Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion
- 264 Downloads
- 3 Citations
Abstract
As process technology continues to shrink, Process Variations and Aging effects have an increasing impact on the reliability and performance of manufactured circuits. Aging effects, namely due to Negative Bias Temperature Instability (NBTI) produce performance degradation as time progresses. This degradation rate depends on a) Operational conditions (e.g., VDD, Temperature and time of electrical stress on MOS transistors) and b) Static technological parameters defined in the fabrication process. Moreover, performance of electronic systems for safety-critical applications which operate for many years in harsh environments are more prompt to be impacted by aging. In order to guarantee a safe operation in advanced technologies, aging monitoring should be performed on chip using built-in aging sensors. The purpose of this work is to present a methodology to determine the correct location for aging sensor insertion, considering the combined impact of process variations (PV) and aging effects (namely due to NBTI). In order to implement the methodology, a path-based statistical timing analysis framework and tools have been developed. It is shown that delay path reordering, associated with PV and aging, may justify the insertion of a few additional sensors, to cover abnormal delays of signal paths that become critical, under long system operation (e.g., 10 years).
Keywords
Aging sensors Error prediction Nanometer technologies Process variations ReliabilityNotes
Acknowledgments
To the CONACYT (México) for the support given through the PhD scholarship nº. 207069/204311. This work has also been partially supported by the European ENIAC SE2A Project, and by Portuguese national funds through FCT – Fundação para a Ciência e a Tecnologia, under project PEst-OE/EEI/LA0021/2011.
References
- 1.Agarwal A, Blaauw D, Zolotov V et al (2003) Statistical delay computation considering spatial correlations. Proc IEEE ASP-DAC, pp. 271–276, JanuaryGoogle Scholar
- 2.Baba AH, Mitra S (2009) Testing for transistor aging. Proc IEEE VLSI Test Symposium (VTS), pp. 215–220Google Scholar
- 3.Borkar S et al (2003) Parameter variation and impact on circuits and microarchitecture. Proc ACM/IEEE Design Automation Conference (DAC), pp. 338–342Google Scholar
- 4.Chan T-B, Sartori J, Gupta P, Kumar R (2011) On the efficacy of NBTI mitigation techniques. Design, Automation & Test in Europe Conference (DATE), pp.1–6Google Scholar
- 5.Martins CV, Semião J, Vazquez JC, Champac V, Santos M, Teixeira IC, Teixeira JP (2011) Adaptive error-prediction flip-flop for performance failure prediction with aging sensors. Proc IEEE VLSI Test Symposium (VTS), pp. 203–208Google Scholar
- 6.Sakurai T, Newton AR (1990) Alpha-power law mosfet model and its application to CMOS inverter delay and other formulas. IEEE J Solid State Circuits 25(2):584–594CrossRefGoogle Scholar
- 7.Siddiqua T, Gurumurthi S, Stan MR (2011) Modeling and analyzing NBTI in the presence of process variations. Proc IEEE Int Symp On Quality Electronic Design (ISQED), pp. 28–35Google Scholar
- 8.Vazquez JC, Champac V, Ziesemer AM Jr, Reis R, Teixeira IC, Santos MB, Teixeira JP (2012) Delay sensing for long-term variations and defects monitoring in safety-critical applications. Analog Integr Circ Sig Process J 70(2):249–263, SpringerCrossRefGoogle Scholar
- 9.Vazquez JC et al (2010) Low sensitivity to process variations aging sensor for automotive safety-critical applications. Proc IEEE VLSI Test Symposium (VTS), pp. 238–243Google Scholar
- 10.Wang W, Cao Y, et al (2007) The impact of NBTI on the performance of combinational and sequential circuits. Proc ACM/IEEE Design Automation Conference (DAC), pp. 364–369, JunGoogle Scholar
- 11.Wang W, Reddy V, Yang B, Balakrishnan V, Krishnan S, Cao Y (2008) Statistical prediction of circuit aging under process variations. Proc IEEE Custom Integrated Circuits Conference (CICC), pp. 13–16Google Scholar
- 12.Wang W, Wei Z, Yang S, Cao Y (2007) An efficient method to identify critical gates under circuit aging. Proc ICCAD, pp. 735–740Google Scholar
- 13.Wang W, Yang Sh, Bhardwaj S, Vrudhula S, Liu F, Cao Y (2010) The impact of NBTI effect on combinational circuit: modeling, simulation, and analysis. IEEE Trans VLSI Syst 18, Nº. 2, FebGoogle Scholar
- 14.Wayne Johnson R et al (2004) The changing automotive environment: high-temperature electronics. IEEE Trans EPM 27(3):164–176Google Scholar