Journal of Electronic Testing

, Volume 26, Issue 6, pp 599–619 | Cite as

On-Chip Delay Measurement Based Response Analysis for Timing Characterization

  • Ramyanshu Datta
  • Antony Sebastine
  • Ashwin Raghunathan
  • Gary Carpenter
  • Kevin Nowka
  • Jacob A. Abraham
Article
First Online:
Received:
Accepted:

Abstract

We present techniques for response analysis for timing characterization, i.e., delay test and debug of Integrated Circuits (ICs), using on-chip delay measurement of critical paths of the IC. Delay fault are a major source of failure in modern ICs designed in Deep Sub-micron technologies, making it imperative to perform delay fault testing on such ICs. Delay fault testing schemes should enable detection of gross as well as small delay faults in such ICs to be efficient. Additionally there is a need for performing efficient and systematic silicon debug for timing related failures. The timing characterization techniques presented in this paper overcome the observability limitations of existing timing characterization schemes in achieving the aforementioned goals, thus enabling quick and efficient timing characterization of DSM ICs. Additionally the schemes have low hardware overhead and are robust in face of process variations.

Keywords

Delay faul testing Small delay defects Parametric failures Design for Test Design for Debug 
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Notes

Acknowledgements

The authors would like to thank Whitney J. Townsend for helping us design the multipliers.

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Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Ramyanshu Datta
    • 1
  • Antony Sebastine
    • 1
  • Ashwin Raghunathan
    • 1
  • Gary Carpenter
    • 2
  • Kevin Nowka
    • 2
  • Jacob A. Abraham
    • 1
  1. 1.Computer Engineering Research CenterThe University of Texas at AustinAustinUSA
  2. 2.IBM ResearchAustinUSA

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