Advertisement

Journal of Electronic Testing

, Volume 26, Issue 3, pp 307–322 | Cite as

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics

  • Stephan EggersglüßEmail author
  • Görschwin Fey
  • Andreas Glowatz
  • Friedrich Hapke
  • Juergen Schloeffel
  • Rolf Drechsler
Article

Abstract

As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to detect small delay defects and to verify the correct temporal behavior of a circuit. In this article, MONSOON, an efficient SAT-based approach for generating non-robust and robust test patterns for path delay faults is presented. MONSOON handles tri-state elements and environmental constraints occurring in industrial practice using multiple-valued logics. Structural techniques increase the efficiency of the algorithm. A comparison with a state-of-the-art approach shows a significant speed-up. Experimental results for large industrial circuits demonstrates the feasibility and robustness of MONSOON.

Keywords

SAT Delay testing ATPG Path delay faults Multiple-valued logics 

Notes

Acknowledgment

This work was supported in part by the German Federal Ministry of Education and Research (BMBF) in the Project MAYA under the contract number 01M3172B and by the German Research Foundation (DFG) under contract number DR 287/15-1.

References

  1. 1.
    Biere A (2008) PicoSAT essentials. J Satisfiab Boolean Model Comput 4:75–97zbMATHGoogle Scholar
  2. 2.
    Chandrasekar K, Hsiao MS (2005) Integration of learning techniques into incremental satisfiability for efficient path-delay fault test generation. In: Proceedings of design, automation and test in Europe, pp 1002–1007Google Scholar
  3. 3.
    Chen C, Gupta SK (1996) A satisfiability-based test generator for path delay faults in combinational circuits. In: Proceedings of the design automation conference, pp 209–214Google Scholar
  4. 4.
    Christou K, Michael MK, Tragoudas S (2008) On the use of ZBDDs for implicit and compact critical path delay fault test generation. J Electron Test Theory Appl 24:203–222CrossRefGoogle Scholar
  5. 5.
    Czutro A, Polian I, Lewis M, Engelke P, Reddy SM, Becker B (2009) TIGUAN: thread-parallel integrated test pattern generator utilizing satisfiability analysis. In: Proceedings of the international conference on VLSI design, pp 227–232Google Scholar
  6. 6.
    Drechsler R (1994) BiTeS: a BDD based test pattern generator for strong robust path delay faults. In: Proceedings of the European conference on design automation, pp 322–327Google Scholar
  7. 7.
    Drechsler R, Eggersglüß S, Fey G, Glowatz A, Hapke F, Schloeffel J, Tille D (2008) On acceleration of SAT-based ATPG for industrial designs. IEEE Trans Comput-Aided Des Circuits Syst 27:1329–1333CrossRefGoogle Scholar
  8. 8.
    Drechsler R, Eggersglüß S, Fey G, Tille D (2009) Test pattern generation using Boolean proof engines. Springer, BerlinzbMATHCrossRefGoogle Scholar
  9. 9.
    Eén N, Sörensson N (2004) An extensible SAT solver. In: Proceedings of the international conference on theory and applications of satisfiability testing. Lecture notes in computer science, vol 2919, pp 502–518Google Scholar
  10. 10.
    Eggersglüß S, Drechsler R (2008) On the influence of Boolean encodings in SAT-based ATPG for path delay faults. In: Proceedings of the international symposium on multiple-valued logic, pp 94–99Google Scholar
  11. 11.
    Eggersglüß S, Drechsler R (2009) Increasing robustness of SAT-based delay test generation using efficient dynamic learning techniques. In: Proceedings of the IEEE European test symposiumGoogle Scholar
  12. 12.
    Eggersglüß S, Fey G, Drechsler R, Glowatz A, Hapke F, Schloeffel J (2007) Combining multi-valued logics in SAT-based ATPG for path delay faults. In: Proceedings of the ACM & IEEE international conference on formal methods and models for codesign, pp 181–187Google Scholar
  13. 13.
    Fey G, Warode T, Drechsler R (2007) Reusing learned information in SAT-based ATPG. In: Proceedings of the international conference on VLSI design, pp 69–76Google Scholar
  14. 14.
    Fuchs K, Fink F, Schulz MH (1991) DYNAMITE: an efficient automatic test pattern generation system for path delay faults. IEEE Trans Comput-Aided Des Circuits Syst 10:1323–1335CrossRefGoogle Scholar
  15. 15.
    Fuchs K, Pabst M, Rössel T (1994) RESIST: a recursive test pattern generation algorithm for path delay faults considering various test classes. IEEE Trans Comput-Aided Des Circuits Syst 13:1550–1562CrossRefGoogle Scholar
  16. 16.
    Goldberg E, Novikov Y (2007) BerkMin: a fast and robust sat-solver. Discrete Appl Math 155:1549–1561zbMATHCrossRefMathSciNetGoogle Scholar
  17. 17.
    Hooker JN (1993) Solving the incremental satisfiability problem. J Log Program 15:177–186zbMATHCrossRefMathSciNetGoogle Scholar
  18. 18.
    Huang ID, Gupta SK (2005) Selection of paths for delay testing. In: Proceedings of the IEEE Asian test symposium, pp 208–215Google Scholar
  19. 19.
    Kim J, Whittemore J, Marques-Silva JP, Sakallah KA (2000) On applying incremental satisfiability to delay fault testing. In: Proceedings of design, automation and test in Europe, pp 380–384Google Scholar
  20. 20.
    Krstić A, Cheng KT (1998) Delay fault testing for VLSI circuits. Kluwer Academic, BostonGoogle Scholar
  21. 21.
    Larrabee T (1992) Test pattern generation using Boolean satisfiability. IEEE Trans Comput-Aided Des Circuits Syst 11:4–15CrossRefGoogle Scholar
  22. 22.
    Lin CJ, Reddy SM (1987) On delay fault testing in logic circuits. IEEE Trans Comput-Aided Des Circuits Syst 6:694–703CrossRefGoogle Scholar
  23. 23.
    Lu F, Wang LC, Cheng KT, Huang R (2003) A circuit SAT solver with signal correlation guided learning. In: Proceedings of design, automation and test in Europe, pp 892–897Google Scholar
  24. 24.
    Lu SY, Hsieh MT, Liou JJ (2007) An efficient SAT-based path delay fault ATPG with an unified sensitization model. In: Proceedings of the international test conferenceGoogle Scholar
  25. 25.
    Marques-Silva JP, Sakallah KA (1997) Robust search algorithms for test pattern generation. In: Proceedings of the international symposium on fault-tolerant computing, pp 152–157Google Scholar
  26. 26.
    Marques-Silva JP, Sakallah KA (1999) GRASP: a search algorithm for propositional satisfiability. IEEE Trans Comput 48:506–521CrossRefMathSciNetGoogle Scholar
  27. 27.
    Moskewicz MW, Madigan CF, Zhao Y, Zhang L, Malik S (2001) Chaff: engineering an efficient SAT solver. In: Proceedings of the design automation conference, pp 530–535Google Scholar
  28. 28.
    Pomeranz I, Reddy SM, Uppaluri P (1995) NEST: a nonenumerative test generation method for path delay faults in combinational circuits. IEEE Trans Comput-Aided Des Circuits Syst 14:1505–1515CrossRefGoogle Scholar
  29. 29.
    Qiu W, Walker DMH (2003) An efficient algorithm for finding the K longest testable paths through each gate in a combinational circuit. In: Proceedings of the international test conference, pp 592–601Google Scholar
  30. 30.
    Schulz MH, Auth E (1989) Improved deterministic test pattern generation with applications to redundancy identification. IEEE Trans Comput-Aided Des Circuits Syst 8:811–816Google Scholar
  31. 31.
    Sentovich EM, Singh KJ, Lavagno L, Moon C, Murgai R, Saldanha A, Savoj H, Stephan PR, Brayton RK, Sangiovanni-Vincentelli AL (1992) SIS: a system for sequential circuit synthesis. Technical report, University of BerkeleyGoogle Scholar
  32. 32.
    Smith GL (1985) Model for delay faults based upon paths. In: Proceedings of the international test conference, pp 342–349Google Scholar
  33. 33.
    Shtrichman O (2001) Pruning techniques for the SAT-based bounded model checking problem. In: Proceedings of the correct hardware design and verification methods. Lecture notes in computer science, vol 2144, pp 58–70Google Scholar
  34. 34.
    Tragoudas S, Karayiannis D (1999) A fast nonenumerative automatic test pattern generator for path delay faults. IEEE Trans Comput-Aided Des Circuits Syst 18:1050–1057CrossRefGoogle Scholar
  35. 35.
    Wang LC, Liou JJ, Cheng KT (2004) Critical path selection for delay fault testing based upon a statistical timing model. IEEE Trans Comput-Aided Des Circuits Syst 23:1550–1565CrossRefGoogle Scholar
  36. 36.
    Yang K, Cheng KT, Wang LC (2004) Trangen: a SAT-based ATPG for path-oriented transition faults. In: Proceedings of the ASP design automation conference, pp 92–97Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Stephan Eggersglüß
    • 1
    Email author
  • Görschwin Fey
    • 1
  • Andreas Glowatz
    • 2
  • Friedrich Hapke
    • 2
  • Juergen Schloeffel
    • 2
  • Rolf Drechsler
    • 1
  1. 1.University of BremenBremenGermany
  2. 2.Mentor Graphics Development GmbHHamburgGermany

Personalised recommendations