Journal of Electronic Testing

, Volume 24, Issue 1–3, pp 57–65 | Cite as

A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique

  • Rui Gong
  • Wei Chen
  • Fang Liu
  • Kui Dai
  • Zhiying Wang
Article
First Online:
Received:
Accepted:

Abstract

Some asynchronous circuit techniques are proposed to provide a new approach to Single Event Effect (SEE) tolerance in synchronous circuits. Two structures, Double Modular Redundancy (DMR) and Temporal Spatial Triple Modular Redundancy with Dual Clock Triggered Register (TSTMR-D), are presented. Three SEE tolerant 8051 cores with DMR, TSTMR-D and traditional Triple Modular Redundancy (TMR) are implemented in SMIC 0.35 μm process. The results of fault injection experiments indicate that DMR has a relatively low overhead on both area and latency than TMR, while tolerates SEU in sequential logic. TSTMR-D provides tolerance for both SEU and SET with reasonable area and latency overhead.

Keywords

SEE tolerance Asynchronous circuit SEU tolerance SET tolerance 
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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Rui Gong
    • 1
  • Wei Chen
    • 1
  • Fang Liu
    • 1
  • Kui Dai
    • 1
  • Zhiying Wang
    • 1
  1. 1.School of ComputerNational University of Defense TechnologyChangshaPR China

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