Journal of Electronic Testing

, Volume 22, Issue 2, pp 151–159 | Cite as

Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults

  • Yu-Chiun Lin
  • Shi-Yu Huang


Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of these block-level techniques are needed in order to successfully diagnose a large chip with multiple faults. In this paper, we present such a strategy. Our strategy is effective in identifying more than one fault accurately. It proceeds in two phases. In the first phase we concentrate on the identification of the so-called structurally independent faults based on a concept referred to as word-level prime candidate, while in the second phase we further trace the locations of the more elusive structural dependent faults. Experimental results show that this strategy is able to find 3 to 4 faults within 10 signal inspections for three real-life designs randomly injected with 5 node-type or stuck-at faults.


fault diagnosis multiple fault diagnosis yield debugging prime candidate 


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  1. 1.
    M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital System Testing and Testable Design, Computer Science Press, 1990.Google Scholar
  2. 2.
    B. Arslan and A. Orailoglu, “Fault Dictionary Size Reduction Through Test Response Superposition,” Proc. of Int’l Conf. on Computer Design, Sept. 2002, pp. 480–485.Google Scholar
  3. 3.
    T. Bartenstein, D. Herberlin, L. Huisman, and D. Sliwinski, “Diagnosing Combinational Logic Design Using the Single Location At-A-Time (SLAT) Paradigm,” Proc. of Int’l Test Conf., 2001, pp. 287–296.Google Scholar
  4. 4.
    B. Boppana, R. Mukherjee, J. Jain, and M. Fujita, “Multiple Error Diagnosis Based On Xlists,” Proc. of Design Automation Conf., June 1999, pp. 100–110.Google Scholar
  5. 5.
    V. Boppana, I. Hartanto, and W.K. Fuchs, “Full Fault Dictionary Storage Based on Labeled Tree Encoding,” Proc. of VLSI Test Symposium, May 1996, pp. 174–179.Google Scholar
  6. 6.
    R.K. Brayton et al., SIS: A System for Sequential Circuit Synthesis, Berkeley, University of California, Tech. Report, 1992.Google Scholar
  7. 7.
    P.Y. Chung, Y.M. Wang, and I.N. Hajj, “Diagnosis and Correction of Logic Design Errors in Digital Circuits,” Proc. of Design Automation Conf., June 1993, pp. 503–508.Google Scholar
  8. 8.
    S.-Y. Huang, K.-T. Cheng, K.-C. Chen, and D.-T. Cheng, “ErrorTracer: A Fault Simulation Based Approach to Design Error Diagnosis,” Proc. of Int’l Test Conf., Nov. 1997, pp. 974–981.Google Scholar
  9. 9.
    S.-Y. Huang, “On Improving The Accuracy of Multiple Fault Diagnosis,” Proc. of VLSI Test Symposium, April 2001, pp. 34–39.Google Scholar
  10. 10.
    S.-Y. Huang, “Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation,” Proc. of VLSI Test Symposium, April 2002, pp. 193–198.Google Scholar
  11. 11.
    J.B. Khare, W. Maly, S. Griep, and D. Schmitt-Landsiedel, “Yield-oriented Computer-Aided Defect Diagnosis,” IEEE Transactions on Semiconductor Manufacturing, May 1995, Vol. 8, no. 2, pp. 195–206.CrossRefGoogle Scholar
  12. 12.
    A. Kuehlmann, D.I. Cheng, A. Srinivasan, and D.P. Lapotin, “Error Diagnosis for Transistor-Level Verification,” Proc. of Design Automation Conf., June 1994, pp. 218–223.Google Scholar
  13. 13.
    D.B. Lavo, T. Larabee, and B. Chess, “Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis,” Proc. of Int’l Test Conference, 1996, pp. 611–619.Google Scholar
  14. 14.
    D.B. Lavo, I. Hartanto, and T. Larrabee, “Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis,” Proc. of Int’l Test Conf., Oct. 2002, pp. 250–259.Google Scholar
  15. 15.
    C. Liu and K. Chakrabarty, “Compact Dictionaries for Fault Diagnosis in Scan-BIST,” IEEE Trans. on Computers, Vol. 5, No. 6, pp. 775–780, June 2004.CrossRefGoogle Scholar
  16. 16.
    J.B. Liu, A. Veneris, and H. Takahashi, “Incremental Diagnosis of Multiple Open-Interconnects,” Proc. of Int’l Test Conf., 2002, pp. 1085–1092.Google Scholar
  17. 17.
    I. Pomeranz, “On Pass/Fail Dictionaries for Scan Circuits,” Prof. of Asian Test Symposium, Nov. 2001, pp. 51–56.Google Scholar
  18. 18.
    I. Pomeranz and S.M. Reddy, “On Correction of Multiple Design Errors,” IEEE Trans. on Computer-Aided Design, Feb. 1995, Vol. 14, pp. 255–264.CrossRefGoogle Scholar
  19. 19.
    J. Richman and K.R. Bowden, “The Modern Fault Dictionary,” Proc. of Int’l Test Conf., Nov. 1985, pp. 696–702.Google Scholar
  20. 20.
    A.G. Veneris and I.N. Hajj, “A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits,” Proc. of Great Lake Symposium on VLSI Design, March 1997, pp. 45–50.Google Scholar
  21. 21.
    J.W, and E.M. Rudnick, “Bridging Fault Diagnosis Using Stuck-At Fault Simulation,” IEEE Trans. on Computer-Aided Design, April 2000, Vol. 19, No. 4, pp. 489–495.Google Scholar
  22. 22.
    A. Veneris, J.B. Liu, A. Amiri, and M.S. Abadir, “Incremental Diagnosis and Correction of Multiple Faults and Errors,” Proc. of IEEE Design, Automation, and Test in Europe, 2002, pp. 716–721.Google Scholar
  23. 23.
    S. Venkataraman and S.B. Drummonds, “A Technique for Logic Fault Diagnosis of Interconnect Open Faults,” Proc. of VLSI Test Symposium, 2000, pp. 313–318.Google Scholar
  24. 24.
    S. Venkataraman and S.B. Drummonds, “POIROT: Applications of a Logic Fault Diagnosis Tool,” IEEE Design & Test of Computers, Vol. 18, No. 1, pp. 19–30, 2001.CrossRefGoogle Scholar
  25. 25.
    J.A. Waicukauski and E. Lindbloom, “Failing Diagnosis of Structured VLSI,” IEEE Design and Test of Computers, Vol. 6, pp. 49–60, Aug. 1989.CrossRefGoogle Scholar
  26. 26.
    Z. Wang, K.H. Tsai, M. Marek-Sadowska, and J. Rajski, “An Efficient and Effective Methodology on the Multiple Fault Diagnosis,” Proc. of Int’l Test Conf., 2003, pp. 329–338.Google Scholar
  27. 27.
    X. Wen, T. Miyoshi, S. Kajiihara, L.-T. Wang, K.K. Saluja, and K. Kinoshita, “On Per-Test Fault Diagnosis Using the X-Fault Model,” Proc. of Int’l Conf. on Computer-Aided Design, 2004, pp. 633–640.Google Scholar

Copyright information

© Springer Science + Business Media, LLC 2006

Authors and Affiliations

  • Yu-Chiun Lin
    • 1
  • Shi-Yu Huang
    • 1
  1. 1.Department of Electrical EngineeringNational Tsing-Hua UniversityROC

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