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Journal of Electronic Testing

, Volume 22, Issue 2, pp 151–159 | Cite as

Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults

  • Yu-Chiun Lin
  • Shi-Yu Huang
Article

Abstract

Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of these block-level techniques are needed in order to successfully diagnose a large chip with multiple faults. In this paper, we present such a strategy. Our strategy is effective in identifying more than one fault accurately. It proceeds in two phases. In the first phase we concentrate on the identification of the so-called structurally independent faults based on a concept referred to as word-level prime candidate, while in the second phase we further trace the locations of the more elusive structural dependent faults. Experimental results show that this strategy is able to find 3 to 4 faults within 10 signal inspections for three real-life designs randomly injected with 5 node-type or stuck-at faults.

Keywords

fault diagnosis multiple fault diagnosis yield debugging prime candidate 

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Copyright information

© Springer Science + Business Media, LLC 2006

Authors and Affiliations

  • Yu-Chiun Lin
    • 1
  • Shi-Yu Huang
    • 1
  1. 1.Department of Electrical EngineeringNational Tsing-Hua UniversityROC

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