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Journal of Electronic Testing

, Volume 22, Issue 2, pp 125–142 | Cite as

Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability

  • Hafizur RahamanEmail author
  • Debesh K. Das
  • Bhargab B. Bhattacharya
Article

Abstract

A technique for implementing totally symmetric Boolean functions using hierarchical modules is presented. First, a simple cellular module is designed for synthesizing unate symmetric functions. The structure is universal, admits a recursive design, and uses only 2-input AND-OR gates. A universal test set of size (n 2/8 + 3n/4) for detecting all single stuck-at faults can be easily determined for an n-input module, where n = 2 k , k ≥ 3. General symmetric functions are then realized following a unate decomposition method. The synthesis procedure guarantees full robust path-delay fault testability in the circuit. Experimental results on several symmetric functions reveal that the hardware cost of the proposed design is low, and the number of paths in the circuit is reduced significantly compared to those of earlier designs. Results on circuit area and delay for a few benchmark examples are also reported.

Keywords

path-delay fault stuck-at fault symmetric boolean function synthesis-for-testability unate function universal tests 

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References

  1. 1.
    D.L. Dietmeyer, “Generating Minimal Covers of Symmetric Function,” IEEE TCAD, Vol. 12, No. 5, pp. 710–713, 1993.Google Scholar
  2. 2.
    W. Ke and P.R. Menon, “Delay-Testable Implementations of Symmetric Functions,” IEEE TCAD, Vol. 14, pp. 772–775, 1995.Google Scholar
  3. 3.
    S. Chakraborty, S. Das, D.K. Das, and B.B. Bhattacharya, “Synthesis of Symmetric Functions for Path-Delay Fault Testability,” IEEE TCAD, Vol. 19, pp. 1076–1081, September 2000.Google Scholar
  4. 4.
    Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, New York, 1977.Google Scholar
  5. 5.
    Y.X. Yang and B. Guo, “Further enumerating boolean functions of cryptographic significance,” J. Cryptology, Vol. 8, No. 3, pp. 115–122, 1995.MathSciNetzbMATHGoogle Scholar
  6. 6.
    S.L. Hurst, “Digital Summation Threshold Logic Gates: A New Circuit Element,” IEE Proc., Vol. 120, No. 11, pp. 1301–1307, 1973.Google Scholar
  7. 7.
    J. Ja′ Ja′ and S.M. Wu, “A New Approach to Realize Partially Symmetric Functions,” Tech. Rep. SRC TR 86–54, Dept. EE, University of Maryland, 1986.Google Scholar
  8. 8.
    H. Rahaman, D.K. Das, and B.B. Bhattacharya, “A Simple Delay-Testable Design of Digital Summation Threshold Logic (DSTL) Array,” in Proc. 5th International Workshop on Boolean Problems, Freiberg, Germany, September 2002.Google Scholar
  9. 9.
    H. Rahaman, D.K. Das, and B.B. Bhattacharya, “A New Synthesis of Symmetric Functions,” in Proc. Int. Conf. ASP-DAC/VLSI Design, 2002, pp. 160–165.Google Scholar
  10. 10.
    E.M. Sentovich, et al., “SIS: A Sequential System for Sequential Circuit Synthesis,” Technical Report UCB/ERL m92/41. Electronic Research Laboratory, University of California, Berkeley, May 1992.Google Scholar
  11. 11.
    M. Perkowski, P. Kerntopf, A.Buller, M.C.-Jeske, A. Mishchenko, X. Song, A. Al-Rabadi, L.Jozwiak, A. Coppola, and B. Massey, “Regularity and Symmetry as a Base for Efficient Realization of Reversible Logic Circuits,” Manuscript, 2001.Google Scholar
  12. 12.
    P. Picton, “Modified Fredkin Gates in Logic Design,” Microelectronics Journal, Vol. 25, pp. 437–441, 1994.CrossRefGoogle Scholar
  13. 13.
    G.L. Smith, “Model for Delay Faults Based Upon Paths,” in Proc. Int. Test Conf., 1985, pp. 342– 349.Google Scholar
  14. 14.
    C.J. Lin and S.M. Reddy, “On Delay Fault Testing in Logic Circuits,” IEEE Trans. CAD, Vol. CAD-6, pp. 694–703, Sept. 1987.Google Scholar
  15. 15.
    R. Betancourt, “Derivation of Minimum Test Sets for Unate Logic circuits,” IEEE Trans. Comput., Vol. C-20, pp. 1264–1269, 1971.MathSciNetGoogle Scholar
  16. 16.
    S. B. Akers, “Universal Test Sets for Logic Networks,” IEEE Trans. Comput., Vol. C-22, pp. 835–839, 1973.MathSciNetCrossRefGoogle Scholar
  17. 17.
    S.M. Reddy, “Complete Test Set for Logic Functions,” IEEE Trans. Comput., Vol. C-22, pp. 1016–1020, Nov. 1973.Google Scholar
  18. 18.
    U. Sparmann, et al., “Minimal Delay Test for Unate Gate Networks,” in Proc. Asian Test Symp., pp. 10–16, 1997.Google Scholar
  19. 19.
    H. Kim and J.P. Hayes, “Realization-Independent ATPG for Designs with Unimplemented Blocks,” IEEE Trans. CAD, Vol. 20, pp. 290–306, Feb. 2001.Google Scholar
  20. 20.
    S. Yang, “Logic Synthesis and Optimization Benchmarks Guide,” Technical Report 1991-IWLS-UG-Saeyang, Microelectronics Center of North Carolina.Google Scholar

Copyright information

© Springer Science + Business Media, LLC 2006

Authors and Affiliations

  • Hafizur Rahaman
    • 1
    Email author
  • Debesh K. Das
    • 2
  • Bhargab B. Bhattacharya
    • 3
  1. 1.Information Technology DepartmentBengal Engineering and Science UniversityHowrahIndia
  2. 2.Computer Science & Engineering DepartmentJadavpur UniversityKolkataIndia
  3. 3.ACM UnitIndian Statistical InstituteKolkataIndia

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