Journal of Electronic Testing

, Volume 22, Issue 1, pp 61–69 | Cite as

Automatic Test Pattern Generation for Resistive Bridging Faults

  • Piet Engelke
  • Ilia Polian
  • Michel Renovell
  • Bernd Becker
Article

Abstract

An ATPG for resistive bridging faults in combinational or full-scan circuits is proposed. It combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced so far, it can handle static effects of arbitrary non-feedback bridges between two nodes, including ones detectable at higher bridge resistance and undetectable at lower resistance, and faults requiring more than one vector for detection. The developed tool is applied to ISCAS circuits, and a higher efficiency compared with other resistive bridging fault as well as stuck-at ATPG is reported. Information required for accurate resistive bridging fault simulation is obtained as a by-product.

Keywords

ATPG resistive short defects bridging faults SAT 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    J.P. Cusey and J.H. Patel, “BART: A Bridging Fault Test Generator for Sequential Circuits,” Int’l Test Conf., 1997, pp. 838–847.Google Scholar
  2. 2.
    P. Engelke, I. Polian, M. Renovell, and B. Becker, “Simulating Resistive Bridging and Stuck-At Faults,” Int’l Test Conf., 2003, pp. 1051–1059.Google Scholar
  3. 3.
    P. Engelke, I. Polian, M. Renovell, B. Seshadri, and B. Becker, “The Pros and Cons of Very-Low-Voltage Testing: An Analysis Based on Resistive Short Defects,” VLSI Test Symp., 2004, pp. 171–178.Google Scholar
  4. 4.
    F.J. Ferguson and J. Shen, “Extraction and Simulation of Realistic CMOS Faults using Inductive Fault Analysis,” Int’l Test Conf., 1988, pp. 475–484.Google Scholar
  5. 5.
    E. Gizdarski and H. Fujiwara, “SPIRIT: A Highly Robust Combinational test Generation Algorithm,” IEEE Trans. on CAD, vol. 21, no. 12, pp. 1446–1458, 2002.Google Scholar
  6. 6.
    G. Greenstein and J. Patel, “E-PROOFS: A CMOS Bridging Fault Simulator,” Int’l Conf. on CAD, pp. 268–271, 1992.Google Scholar
  7. 7.
    I. Hamzaoglu and J. Patel, “New Techniques for Deterministic Test Pattern Generation,” Journal of Electronic Testing: Theory and Applications, vol. 15, pp. 63–73, 1999.CrossRefGoogle Scholar
  8. 8.
    H. Hao and E. McCluskey, “Resistive Shorts Within CMOS Gates,” Int’l Test Conf., pp. 292–301, 1991,Google Scholar
  9. 9.
    C. Lee and D.M.H. Walker, “PROBE: A PPSFP Simulator for Resistive Bridging Faults,” VLSI Test Symp., 2000, pp. 105–110.Google Scholar
  10. 10.
    Z. Li, X. Lu, W. Qiu, W. Shi, and D. Walker, “A Circuit Level Fault Model for Resistive Bridges,” ACM Trans. on Design Automation of Electronic Systems, vol. 8, no. 4, pp. 546–559,2003.CrossRefGoogle Scholar
  11. 11.
    Y. Liao and D. Walker, “Fault Coverage Analysis for Physically-based CMOS Bridging Faults at Different Power Supply Voltages,” Int’l Test Conf., 1996, pp. 767–775.Google Scholar
  12. 12.
    T. Maeda and K. Kinoshita, “Precise Test Generation for Resistive Bridging Faults of CMOS Combinational Circuits,” Int’l Test Conf., 2000, pp. 510–519.Google Scholar
  13. 13.
    W. Moore, G. Gronthoud, K. Baker, and M. Lousberg, “Delay-fault Testing and Defects in Deep Sub-micron—Does Critical Resistance Really Mean Anything,” Int’l Test Conf., 2000, pp. 95–104.Google Scholar
  14. 14.
    M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik, “Chaff: Engeneering an Efficient SAT Solver,” Design Automation Conf., 2001.Google Scholar
  15. 15.
    I. Polian, P. Engelke, M. Renovell, and B. Becker, “Modelling Feedback Bridging Faults With Non-Zero Resistance,” European Test Workshop, 2003, pp. 91–96.Google Scholar
  16. 16.
    M. Renovell, F. Azaïs, and Y. Bertrand, “Detection of Defects Using Fault Model Oriented Test Sequences,” Journal of Electronic Testing: Theory and Applications, vol. 14, pp. 13–22, 1999.CrossRefGoogle Scholar
  17. 17.
    M. Renovell, P. Huc, and Y. Bertrand, “CMOS Bridge Fault Modeling,” VLSI Test Symp., 1994, pp. 392–397.Google Scholar
  18. 18.
    M. Renovell, P. Huc, and Y. Bertrand, “The Concept of Resistance Interval: A New Parametric Model for Resistive Bridging Fault,” VLSI Test Symp., 1995, pp. 184–189.Google Scholar
  19. 19.
    M. Renovell, P. Huc, and Y. Bertrand, “Bridging Fault Coverage Improvement by Power Supply Control,” VLSI Test Symp., 1996, pp. 338–343.Google Scholar
  20. 20.
    R. Rodríguez-Montañés, E. Bruls, and J. Figueras, “Bridging Defects Resistance Measurements in a CMOS Process,” Int’l Test Conf., 1992, pp. 892–899.Google Scholar
  21. 21.
    V. Sar-Dessai and D. Walker, “Accurate Fault Modeling and Fault Simulation of Resistive Bridges,” Int. Symp. Defect and Fault Tolerance in VLSI Systems, 1998, pp. 102–107.Google Scholar
  22. 22.
    V. Sar-Dessai and D. Walker, “Resistive Bridge Fault Modeling, Simulation and Test Generation,” Int’l Test Conf., 1999, pp. 596–605.Google Scholar
  23. 23.
    T. Shinogi, T. Kanbayashi, T. Yoshikawa, S. Tsuruoka, and T. Hayashi, “Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems,” Asian Test Symp., 2001, pp. 76–81.Google Scholar
  24. 24.
    M. Spica, M. Tripp, and R. Roeder, “A New Understanding of Bridge Defect Resistances and Process Interactions from Correlating Inductive Fault Analysis Predictions to Empirical Test Results,” IEEE Int’l Workshop on Current and Defect-Based Testing, 2001, pp. 11–16.Google Scholar

Copyright information

© Springer Science + Business Media, Inc 2006

Authors and Affiliations

  • Piet Engelke
    • 1
  • Ilia Polian
    • 1
  • Michel Renovell
    • 2
  • Bernd Becker
    • 1
  1. 1.Institute of Computer ScienceAlbert-Ludwigs-UniversityFreiburg im BreisgauGermany
  2. 2.LIRMM – UMIIMontpellierFrance

Personalised recommendations