Journal of Electronic Testing

, Volume 21, Issue 5, pp 539–549 | Cite as

Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2 m )

  • Chiou-Yng Lee
  • Che Wun Chiou
  • Jim-Min Lin


The finite field is widely used in error-correcting codes and cryptography. Among its important arithmetic operations, multiplication is identified as the most important and complicated. Therefore, a multiplier with concurrent error detection ability is elegantly needed. In this paper, a concurrent error detection scheme is presented for bit-parallel systolic dual basis multiplier over GF(2 m ) according to the Fenn’s multiplier in [7]. Although, the proposed method increases the space complexity overhead about 27% and the latency overhead about one extra clock cycle as compared to Fenn’s multiplier. Our analysis shows that all single stuck-at faults can be detected concurrently.


finite fields multiplier fault-tolerant computing fault detection cryptography single stuck-at fault 


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  1. 1.
    B. Benjauthrit and I.S. Reed, “Galois Switching Functions and Their Applications,” IEEE Trans. Computers, vol. C-25, pp. 78–86, 1976.Google Scholar
  2. 2.
    G. Bertoni, L. Breveglieri, I. Koren, P. Maistri, and V. Piuri, “Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard,” IEEE Trans. Computers, vol. 52, no. 4, pp. 492–505, 2003.CrossRefGoogle Scholar
  3. 3.
    R.E. Blahut, Fast Algorithms for Digital Signal Processing, Reading, Mass.: Addison-Wesley, 1985.Google Scholar
  4. 4.
    D. Boneh, R.A. DeMillo, R.J. Lipton, “On the Importance of Eliminating Errors in Cryptographic Computations,” Journal of Cryptology, vol. 14, pp. 101–119, 2001.CrossRefGoogle Scholar
  5. 5.
    C.W. Chiou, “Concurrent Error Detection in Array Multipliers for GF(2m) Fields,” IEE Electronics Letters, vol. 38, no. 14, pp. 688–689, 2002.CrossRefGoogle Scholar
  6. 6.
    C.W. Chiou, L.C. Lin, F.H. Chou, and S.F. Shu, “Low Complexity Finite Field Multiplier Using Irreducible Trinomials,” Electronics Letters, vol. 39, no. 24, pp. 1709–1711, 2003.CrossRefGoogle Scholar
  7. 7.
    S.T.J. Fenn, M. Benaissa, and O. Taylor, “Dual Basis Systolic Multipliers for GF(2m),” IEE Computers and Digital Techniques, vol. 144, no. 1, pp. 43–46, 1997.CrossRefGoogle Scholar
  8. 8.
    S. Fenn, M. Gossel, M. Benaissa, and D. Taylor, “On-Line Error Detection for Bit-Serial Multipliers in GF(2m),” Journal of Electronic Testing: Theory and Applications, vol. 13, pp. 29–40, 1998.Google Scholar
  9. 9.
    M. Joye, A.K. Lenstra, J.-J. Quisquater, “Chinese Remaindering Based Cryptosystems in the Presence of Faults,” Journal of Cryptology, vol. 12, pp. 241–245, 1999.CrossRefGoogle Scholar
  10. 10.
    R. Karri, G. Kuznetsov, and M. Goessel, “Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers,” in Proc. of CHES 2003, Springer LNCS 2779, pp. 113–124, 2003.Google Scholar
  11. 11.
    Ç.K. Koç and B. Sunar, “Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields,” IEEE Trans. Computers, vol. 47, no. 3, pp. 353–356, 1998.CrossRefGoogle Scholar
  12. 12.
    P.K. Lala, Fault Tolerant and Fault Testable Hardware Design. Prentice Hall, 1985.Google Scholar
  13. 13.
    C.Y. Lee, “Low Complexity Bit-Parallel Systolic Multiplier Over GF(2m) Using Irreducible Trinomials,” IEE Proc.-Comput. Digit. Tech., vol. 150, no. 1, pp. 39–42, 2003.CrossRefGoogle Scholar
  14. 14.
    C.Y. Lee, “Low-Latency Bit-Parallel Systolic Multiplier for Irreducible xm+xn+1 with gcd(m,n) = 1,” IEICE Transactions on Fundamentals, vol. E86-A, no. 11, pp. 2844–2852, 2003.Google Scholar
  15. 15.
    C.Y. Lee, E.H. Lu, and L.F. Sun, “Low-Complexity Bit-Parallel Systolic Architecture for Computing AB2 + C in a Class of Finite Field GF(2m),” IEEE Trans. Circuits and Systems II, pp. 519–523, 2001.Google Scholar
  16. 16.
    C.Y. Lee, E.H. Lu, and J.Y. Lee, “Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally-Spaced Polynomials,” IEEE Trans. Computers, vol. 50, no. 5, pp. 385–393, 2001.CrossRefGoogle Scholar
  17. 17.
    R. Lidl and H. Niederreiter, Introduction to Finite Fields and Their Applications, New York: Cambridge Univ. Press, 1994.Google Scholar
  18. 18.
    F.J. MacWilliams and N.J.A. Sloane, The Theory of Error-Correcting Codes, Amsterdam: North-Holland, 1977.Google Scholar
  19. 19.
    E.D. Mastrovito, “VLSI Architectures for Multiplication Over Finite Field GF(2m),” Applied Algebra, Algebraic Algorithms, and Error-Correcting Codes, in Proc. Sixth Int’l Conf., AAECC-6, T. Mora (ed.), Rome, pp. 297–309, July 1988.Google Scholar
  20. 20.
    A.J. Menezes (ed.), Applications of Finite Fields, Boston: Kluwer Academic, 1993.Google Scholar
  21. 21.
    J.H. Patel and L.Y. Fung, “Concurrent Error Detection in ALU’s by Recomputing with Shifted Operands,” IEEE Trans. Computers, vol. C-31, no. 7, pp. 589–595, 1982.Google Scholar
  22. 22.
    J.H. Patel and L.Y. Fung, “Concurrent Error Detection in Multiply and Divide Arrays,” IEEE Trans. Computers, vol. C-32, no. 4, pp. 417–422, 1983.Google Scholar
  23. 23.
    I.S. Reed and T.K. Truong, “The Use of Finite Fields to Compute Convolutions,” IEEE Trans. Information Theory, vol. IT-21, no. 2, pp. 208–213, 1975.CrossRefGoogle Scholar
  24. 24.
    A. Reyhani-Masoleh and M.A. Hasan, “Error Detection in Polynomial Basis Multipliers Over Binary Extension Fields,” in Proc. of Cryptographic Hardware and Embedded Systems-CHES 2002, LNCS 2523, pp. 515–528, 2003.Google Scholar
  25. 25.
    C.L. Wang and J.L. Lin, “Systolic Array Implementation of Multipliers for GF(2m),” IEEE Trans. Circuits and Systems II, vol. 38, pp. 796–800, 1991.CrossRefGoogle Scholar
  26. 26.
    C.C. Wang and D. Pei, “A VLSI Design for Computing Exponentiation in GF(2m) and its Application to Generate Pseudorandom Number Sequences,” IEEE Trans. Computers, vol. 39, no. 2, pp. 258–262, 1990.CrossRefGoogle Scholar
  27. 27.
    C.S. Yeh, S. Reed, and T.K. Truong, “Systolic Multipliers for Finite Fields GF(2m),” IEEE Trans. Computers, vol. C-33, pp. 357–360, 1984.Google Scholar

Copyright information

© Springer Science + Business Media, Inc. 2005

Authors and Affiliations

  1. 1.Program Coordination DepartmentChunghwa Telecommunication LaboratoriesChung-Li, Tao-YuanR.O.C.
  2. 2.Department of Information and Computer ScienceChing Yun UniversityChung-Li, TaoyuanR.O.C.
  3. 3.Department of Information EngineeringFeng Chia UniversityTaichung CityR.O.C.

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