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Journal of Electronic Testing

, Volume 21, Issue 5, pp 539–549 | Cite as

Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2 m )

  • Chiou-Yng Lee
  • Che Wun Chiou
  • Jim-Min Lin
Article

Abstract

The finite field is widely used in error-correcting codes and cryptography. Among its important arithmetic operations, multiplication is identified as the most important and complicated. Therefore, a multiplier with concurrent error detection ability is elegantly needed. In this paper, a concurrent error detection scheme is presented for bit-parallel systolic dual basis multiplier over GF(2 m ) according to the Fenn’s multiplier in [7]. Although, the proposed method increases the space complexity overhead about 27% and the latency overhead about one extra clock cycle as compared to Fenn’s multiplier. Our analysis shows that all single stuck-at faults can be detected concurrently.

Keywords

finite fields multiplier fault-tolerant computing fault detection cryptography single stuck-at fault 

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Copyright information

© Springer Science + Business Media, Inc. 2005

Authors and Affiliations

  1. 1.Program Coordination DepartmentChunghwa Telecommunication LaboratoriesChung-Li, Tao-YuanR.O.C.
  2. 2.Department of Information and Computer ScienceChing Yun UniversityChung-Li, TaoyuanR.O.C.
  3. 3.Department of Information EngineeringFeng Chia UniversityTaichung CityR.O.C.

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