Advertisement

Springer Nature is making Coronavirus research free. View research | View latest news | Sign up for updates

An analytical model of the surface-potential-based source-pocket-doped cylindrical-gate tunnel FET with a work-function-modulated metal gate

  • 4 Accesses

Abstract

A new surface-potential-based analytical model for a source-pocket-doped cylindrical-gate tunnel field-effect transistor (FET) with a work-function-modulated metal gate is proposed herein. The inclusion of a highly doped source pocket layer improves the drain current by two decades because of the higher band-to-band tunneling probability of charge carriers in the vicinity of the tunneling junction. Also, the presence of the work-function-modulated cylindrical gate reduces the subthreshold swing (SS) further below 60 mV/decade and thus enhances the \(I_{60}\) performance. The potential distribution of the model is determined using the two-dimensional (2D) Poisson equation with appropriate boundary conditions and plays a significant role in the calculation of the shortest tunneling distance and the drain current. The position and width of the pocket layer in the source region are optimized with the aim of achieving the maximum current switching ratio (ION/IOFF) and \(I_{60}\) and least possible subthreshold swing. Due to its high current switching ratio, significantly improved \(I_{60}\), and remarkably low SS characteristics, the proposed model represents one of the probable devices to replace complementary metal–oxide–semiconductor (CMOS) technology. The results of the analytical model are validated against those obtained using the Synopsys technology computer-aided design (TCAD) device simulator.

This is a preview of subscription content, log in to check access.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14

References

  1. 1.

    Verhulst, A.S., SoreÌ’e, B., Leonelli, D., Vandenberghe, W.G., Groeseneken, G.: Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor. J. Appl. Phys. 107, 024518-1-8 (2010)

  2. 2.

    Narang, R., Saxena, M., Gupta, R.S., Gupta, M.: Drain current model for a gate all around (GAA) pnpn tunnel FET. Microelectron. J. 44, 479–488 (2013)

  3. 3.

    Shao, Q., Zhao, C., Wu, C., Zhang, J., Zhang, L., Yu, Z.: Compact model and projection of silicon nanowire tunneling transistors (NW-tFETs). In: Proceedings of IEEE International Conference of Electron Devices and Solid-State Circuits, pp. 1–2 (2013)

  4. 4.

    Vishnoi, R., Kumar, M.J.: Compact analytical drain current model of gate-all-around nanowire tunneling FET. IEEE Trans. Electron Devices 61, 2599–2603 (2014)

  5. 5.

    Dash, S., Mishra, G.P.: A 2-D analytical cylindrical gate tunnel FET (CG-TFET) model: impact of shortest tunneling distance. Adv. Nat. Sci. Nanosci. Nanotechnol. 6, 035005-1-10 (2015)

  6. 6.

    Dash, S., Mishra, G.P.: A new analytical threshold voltage model of cylindrical gate tunnel FET (CG-TFET). Superlattices Microstruct. 86, 211–220 (2015)

  7. 7.

    Vishnoi, R., Kumar, M.J.: A pseudo 2D-analytical model of dual material gate all-around nanowire tunneling FET. IEEE Trans. Electron Devices 61, 2264–2270 (2014)

  8. 8.

    Samuel, T.S.A., Balamurugan, N.B., Sibitha, S., Saranya, R., Vanisri, D.: Analytical modeling and simulation of dual material gate tunnel field effect transistors. J. Electr. Eng. Technol. 8, 247–253 (2013)

  9. 9.

    Tsui, B.Y., Huang, C.F.: Wide range work function modulation of binary alloys for MOSFET application. IEEE Electron Device Lett. 24, 153–155 (2003)

  10. 10.

    Manna, B., Sarkhel, S., Islam, N., Sarkar, S., Sarkar, S.K.: Spatial composition grading of binary metal alloy gate electrode for short-channel SOI/SON MOSFET application. IEEE Trans. Electron Devices 59, 3280–3287 (2012)

  11. 11.

    Deb, S., Singh, N.B., Islam, N., Sarkar, S.K.: Work function engineering with linearly graded binary metal alloy gate electrode for short channel SOI MOSFET. IEEE Trans. Nanotechnol. 11, 472–478 (2012)

  12. 12.

    Cristen, H.M., Rouleau, C.M., Ohkubo, I., Zhai, H.Y., Lee, H.N., Sathyamurthy, S., Lowndes, D.H.: An improved continuous compositional-spread technique based on pulsed-laser deposition and applicable to large substrate areas. Rev. Sci. Instrum. 74, 4058–4062 (2003)

  13. 13.

    Ohkubo, I., Christen, H.M., Khalifah, P., Sathyamurthy, S., Zhai, H.Y., Rouleau, C.M., Mandrus, D.G., Lowndes, D.H.: Continuous composition-spread thin films of transition metal oxides by pulsed laser deposition. Appl. Surf. Sci. 223, 35–38 (2004)

  14. 14.

    Pan, A., Liu, R., Sun, M., Ning, C.Z.: Spatial composition grading of quaternary ZnCdSSe alloy nanowires with tunable light emission between 350 and 710 nm on a single substrate. ACS Nano 4, 671–680 (2010)

  15. 15.

    Dash, S., Sahoo, G.S., Mishra, G.P.: Subthreshold swing minimization of cylindrical tunnel FET using binary metal alloy gate. Superlattices Microstruct. 91, 105–111 (2016)

  16. 16.

    Bhuwalka, K.K., Schulze, J., Eisele, I.: Scaling the vertical tunnel FET with tunnel bandgap modulation and gate work-function engineering. IEEE Trans. Electron Devices 52, 909–917 (2005)

  17. 17.

    Verhulst, S., Vandenberghe, W.G., Maex, K., Gendt, S.D., Heyns, M.M., Groeseneken, G.: Complementary silicon-based heterostructure tunnel-FETs with high tunnel rates. IEEE Electron Device Lett. 29, 1398–1401 (2008)

  18. 18.

    Knoch, J., Appenzeller, J.: Modeling of high-performance p-type III–V heterojunction tunnel FETs. IEEE Electron Device Lett. 31, 305–307 (2010)

  19. 19.

    Hosseini, S.E., Moghaddam, M.K.: Analytical modeling of a pnin tunneling field effect transistor. Mater. Sci. Semicond. Process. 30, 56–61 (2015)

  20. 20.

    Boucart, K., Ionescu, A.M.: Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans. Electron Devices 54, 1725–1733 (2007)

  21. 21.

    Dash, S., Jena, B., Kumari, P., Mishra, G.P.: An analytical nanowire tunnel FET (NW-TFET) model with high-κ dielectric to improve the electrostatic performance. In: Proceedings of IEEE Power, Communication and Information Technology Conference, pp. 447–451 (2015)

  22. 22.

    Ionescu, A.M., Riel, H.: Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–337 (2011)

  23. 23.

    Vandenberghe, W.G., Verhulst, A.S., Soree, B., Magnus, W., Groeseneken, G., Smets, Q., Heyns, M., Fischetti, M.V.: Figure of merit for and identification of sub-60 mV/decade devices. Appl. Phys. Lett. 102, 013510-1-4 (2013)

  24. 24.

    Dash, S., Jena, B., Mishra, G.P.: A new analytical drain current model of cylindrical gate silicon tunnel FET with source δ-doping. Superlattices Microstruct. 97, 231–241 (2016)

  25. 25.

    Jhaveri, R., Nagavarapu, V., Woo, J.C.S.: Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor. IEEE Trans. Electron Devices 58, 80–86 (2011)

  26. 26.

    Schubert, E.F.: Delta doping of III–V compound semiconductors: fundamentals and device applications. J. Vac. Sci. Technol. A 8, 2980–2996 (1990)

  27. 27.

    Sciana, B., Radziewicz, D., Paszkiewicz, B., Tlaczala, M., Utko, M., Sitarek, P., Sek, G., Misiewicz, J., Kinder, R., Kovac, J., Srnanek, R.: MOVPE technology and characterisation of silicon δ-doped GaAs and AlxGa1−xAs. Thin Solid Films 412, 55–59 (2002)

  28. 28.

    Kim, P., Lee, K.M., Lee, E.W., Jo, Y., Kim, D.H., Kim, H.J., Yang, K.Y., Son, H., Choi, H.C.: A delta-doped amorphous silicon thin-film transistor with high mobility and stability. J. Korean Phys. Soc. 61, 1835–1839 (2012)

  29. 29.

    Sentaurus Device User Guide. Synopsys, Inc., Mountain View, USA (2014)

  30. 30.

    Streetman, B., Banerjee, S.K.: Solid State Electronic Devices, 6th edn. PHI Publication, New Delhi (2009)

  31. 31.

    Chen, Z.X., Yu, H.Y., Singh, N., Shen, N.S., Sayanthan, R.D., Lo, G.Q., Kwong, D.L.: Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires. IEEE Electron Device Lett. 30, 754–756 (2009)

  32. 32.

    Nabatame, T., Nunoshige, Y., Kadoshima, M., Takaba, H., Segawa, K., Kimura, S., Satake, H., Ota, H., Ohishi, T., Toriumi, A.: Changes in effective work function of HfxRu1−x alloy gate electrode. Microelectron. Eng. 85, 1524–1528 (2008)

  33. 33.

    Matsukawa, T., Liu, Y.X., Masahara, M., Ishii, K., Endo, K., Yamauchi, H., Sugimata, E., Takashima, H., Higashino, T., Suzuki, E., Kanemaru, S.: Work function controllability of metal gates made by interdiffusing metal stacks with low and high work functions. Microelectron. Eng. 80, 284–287 (2005)

  34. 34.

    Gholizadeh, M., Hosseini, S.E.: A 2-D analytical model for double-gate tunnel FETs. IEEE Trans. Electron Devices 61, 1494–1500 (2014)

  35. 35.

    Kane, E.O.: Zener tunneling in semiconductors. J. Phys. Chem. Solids 12, 181–188 (1960)

Download references

Author information

Correspondence to Guru Prasad Mishra.

Ethics declarations

Conflict of interest

The authors declare that they have no conflicts of interest.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Dash, S., Mishra, G.P. An analytical model of the surface-potential-based source-pocket-doped cylindrical-gate tunnel FET with a work-function-modulated metal gate. J Comput Electron (2020). https://doi.org/10.1007/s10825-020-01465-x

Download citation

Keywords

  • Work-function engineering
  • Pocket doping
  • Current switching ratio
  • \(I_{60}\)