Advertisement

TCAD simulations and accurate extraction of reliability-aware statistical compact models

  • Jie DingEmail author
  • Asen Asenov
Article
  • 14 Downloads

Abstract

In this paper, we focus on the TCAD simulation and accurate compact model extraction of the time evolution of statistical variability in conventional (bulk) CMOS transistors, due to bias temperature instability (BTI). The 25-nm physical gate length MOSFETs, typical for 20 nm bulk CMOS technology, are used as test-bed transistors to illustrate our approach. Statistical physical simulations of fresh devices and devices at initial, middle and final stages of BTI degradation are performed and the corresponding nominal and statistical compact models are extracted using a two-stage extraction strategy. The extracted compact models not only accurately capture time evolution of the statistical distribution of the key MOSFET figures of merit, but also the complex correlations between them. An excellent agreement with the original physical TCAD simulation results provides a high degree of confidence that the extracted compact models deliver accurate representation of the operation of each device for the purposes of reliable circuit simulation and verification.

Keywords

Compact model Statistical variability BTI MOSFET 

Notes

References

  1. 1.
    Weckx, P., Kaczer, B., Chen, C., Raghavan, P., Linten, D., Mocuta, A.: Relaxation of time-dependent NBTI variability and separation from RTN. In: 2017 IEEE International Reliability Physics Symposium (IRPS), pp. XT-9.1–XT-9.5 (2017)Google Scholar
  2. 2.
    Asenov, A., Kaya, S., Brown, A.R.: Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness. IEEE Trans. Electron Devices 50, 1254–1260 (2003)CrossRefGoogle Scholar
  3. 3.
    Huang, R., Jiang, X.B., Guo, S.F., Ren, P.P., Hao, P., Yu, Z.Q., et al.: Variability- and reliability-aware design for 16/14 nm and beyond technology. In: 2017 IEEE International Electron Devices Meeting (IEDM), pp. 12.4.1–12.4.4 (2017)Google Scholar
  4. 4.
    Wang, X., Cheng, B., Reid, D., Pender, A., Asenov, P., Millar, C., et al.: FinFET centric variability-aware compact model extraction and generation technology supporting DTCO. IEEE Trans. Electron Devices 62, 3139–3146 (2015)CrossRefGoogle Scholar
  5. 5.
    Zagni, N., Puglisi, F.M., Verzellesi, G., Pavan, P.: threshold voltage statistical variability and its sensitivity to critical geometrical parameters in ultrascaled InGaAs and silicon FETs. IEEE Trans. Electron Devices 64, 4607–4614 (2017)CrossRefGoogle Scholar
  6. 6.
    Amoroso, S.M., Gerrer, L., Asenov, A.: 3D TCAD statistical analysis of transient charging in BTI degradation of nanoscale MOSFETs. In: 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 5–8 (2013)Google Scholar
  7. 7.
    Markov, S., Amoroso, S.M., Gerrer, L., Adamu-Lema, F., Asenov, A.: Statistical interactions of multiple oxide traps under BTI stress of nanoscale MOSFETs. IEEE Electron Device Lett. 34, 686–688 (2013)CrossRefGoogle Scholar
  8. 8.
    Grasser, T., Reisinger, H., Wagner, P.J., Schanovsky, F., Goes, W., Kaczer, B.: The time dependent defect spectroscopy (TDDS) for the characterization of the bias temperature instability. In: 2010 IEEE International Reliability Physics Symposium (IRPS), pp. 16–25 (2010)Google Scholar
  9. 9.
    Diaz-Fortuny, J., Martin-Martinez, J., Rodriguez, R., Nafria, M., Castro-Lopez, R., Roca, E., et al.: TARS: a toolbox for statistical reliability modeling of CMOS devices. In: 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), pp. 1–4 (2017)Google Scholar
  10. 10.
    Kaczer, B., et al.: Origin of NBTI variability in deeply scaled pFETs. In: IEEE International Reliability Physics Symposium, Proceedings, pp. 26–32 (2010)Google Scholar
  11. 11.
    Diaz-Fortuny, J., Martin-Martinez, J., Rodriguez, R., Castro-Lopez, R., Roca, E., Aragones, X., et al.: A versatile CMOS transistor array IC for the statistical characterization of time-zero variability, RTN, BTI, and HCI. IEEE J. Solid State Circuits 54, 476–488 (2019)CrossRefGoogle Scholar
  12. 12.
    Adamu-Lema, F., Wang, X., Amoroso, S.M., Gerrer, L., Millar, C., Asenov, A.: Comprehensive ‘atomistic’ simulation of statistical variability and reliability in 14 nm generation FinFETs. In: 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 157–160 (2015)Google Scholar
  13. 13.
    Diaz-Fortuny, J., Martin-Martinez, J., Rodriguez, R., Nafria, M., Castro-Lopez, R., Roca, E., et al.: CMOS characterization and compact modelling for circuit reliability simulation. In: 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 139–142 (2018)Google Scholar
  14. 14.
    Ding, J., Reid, D., Campbell, M., Asenov, A.: An accurate compact modelling approach for statistical ageing and reliability. In: 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 57–60 (2013)Google Scholar
  15. 15.
    Ding, J.: Accurate CMOS compact model and the corresponding circuit simulation in the presence of statistical variability and ageing. Ph.D. thesis, the University of Glasgow (2015)Google Scholar
  16. 16.
    Frank, W.F.J., Berry, B.S.: Lattice location and atomic mobility of implanted boron in silicon. Radiat. Eff. Defects Solids 21, 105–111 (1974)CrossRefGoogle Scholar
  17. 17.
    Masaharu, T., Tohru, O., Naofumi, O.: A new algorithm for threw-dimensional Voronoi tessellation. J. Comput. Phys. 51, 191–207 (1983)MathSciNetCrossRefGoogle Scholar
  18. 18.
    Brown, A.R., Huard, V., Asenov, A.: Statistical simulation of progressive NBTI degradation in a 45-nm technology pMOSFET. IEEE Trans. Electron Devices 57, 2320–2323 (2010)CrossRefGoogle Scholar
  19. 19.
  20. 20.
    Binjie, C., Dideban, D., Moezi, N., Millar, C., Roy, G., Xingsheng, W., et al.: Statistical-variability compact-modeling strategies for BSIM4 and PSP. IEEE Des. Test Comput. 27, 26–35 (2010)Google Scholar
  21. 21.
    Chaparala, P., Shibley, J., Lim, P.: Threshold voltage drift in PMOSFETS due to NBTI and HCI. In: 2000 IEEE International Integrated Reliability Workshop Final Report, pp. 95–97 (2000)Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.College of Electrical and Power EngineeringTaiyuan University of TechnologyTaiyuanChina
  2. 2.Device Modeling Group, School of EngineeringUniversity of GlasgowGlasgowUK

Personalised recommendations