Journal of Computational Electronics

, Volume 18, Issue 4, pp 1490–1500 | Cite as

Analytical modeling for static and dynamic response of organic pseudo all-p inverter circuits

  • Neha Mishra
  • Poornima MittalEmail author
  • Brijesh Kumar


This paper presents the performance analysis of an all-p-organic pseudo-inverter circuit using dual gate organic thin film transistors. The proposed inverter design has shown significantly high performance in terms of noise margin, gain and propagation delay, leading to the design of more robust digital circuits that, too, exhibit augmented performance. The parameters of the all-p-organic pseudo-inverter are compared with those of zero-Vgs load logic (ZVLL) and dynamic load logic based conventional inverters, and a substantial improvement is found for the novel combination of a dual gate flexible TFT with a pseudo-design. Performance parameters were deeply analyzed, and we observed that the noise margin is improved by 42.8% as compared to ZVLL based conventional inverters. A bootstrap technique was implemented to further improve the performance and reduce the threshold voltage drop. The performance parameters were analyzed mathematically and compared with simulated values. The static as well as dynamic characteristics of organic pseudo-all-p inverter, with and without bootstrap technique, were observed. Static power consumption of the organic pseudo-all-p inverter was estimated. In this way, improvement of noise margin by the bootstrap circuit of the organic pseudo-inverter is characterized. The reduced threshold voltage applied to design of low power circuits enables longer power backup for various applications.


Bootstrapping Dual gate Noise margin Organic pseudo-inverter Organic thin film transistor Power consumption 



  1. 1.
    Kumar, B., Kaushik, B.K., Negi, Y.S., Goswami, V.: Single and dual gate OTFTs based robust organic digital design. Microelectron. Reliab. 54(1), 100–109 (2014)CrossRefGoogle Scholar
  2. 2.
    Mittal, P., Negi, Y.S., Singh, R.K.: Mapping of performance limiting issues to analyze top and bottom contact organic thin film transistors. J. Comput. Electron. 14(1), 360–379 (2015)CrossRefGoogle Scholar
  3. 3.
    Kaushik, B.K., Kumar, B., Prajapati, S., Mittal, P.: Organic Thin-Film Transistor Applications: Materials to Circuits. CRC Press, Boca Raton (2016)CrossRefGoogle Scholar
  4. 4.
    Kumar, B., Kaushik, B.K., Negi, Y.S.: Static and dynamic characteristics of dual gate organic TFT based NAND and NOR circuits. J. Comput. Electron. 13(3), 1–12 (2014)CrossRefGoogle Scholar
  5. 5.
    Chen, Y., Geng, D., Mativenga, M., Nam, H., Jang, J.: High-speed pseudo-CMOS circuits using bulk accumulation a-IGZO TFTs. IEEE Electron Device Lett. 36(2), 153–155 (2014)CrossRefGoogle Scholar
  6. 6.
    Zhao, Q., Liu, Y., Zhao, J., Guo, X., Li, H., Yang, H.: Noise margin modelling for zero-VGS load TFT circuits and yield estimation. IEEE Trans. Electron Devices 63(2), 684–690 (2016)CrossRefGoogle Scholar
  7. 7.
    Mittal, P., Negi, Y.S., Singh, R.K.: An analytical approach for parameter extraction in linear and saturation regions of top and bottom contact organic transistors. J. Comput. Electron. 14(3), 828–843 (2015)CrossRefGoogle Scholar
  8. 8.
    Atlas User’s Manual: Device Simulation Software. Silvaco International, Santa Clara (2010)Google Scholar
  9. 9.
    Huang, T.C., et al.: Pseudo-CMOS: a design style for low-cost and robust flexible electronics. IEEE Trans. Electron Devices 58(1), 141–150 (2011)CrossRefGoogle Scholar
  10. 10.
    Zhao, Q., Sun, W., Zhao, J., Feng, L., Xu, X., Liu, W.: Noise margin, delay, and power model for pseudo-CMOS TFT logic circuits. IEEE Trans. Electron Devices 64(6), 2635–2641 (2017)CrossRefGoogle Scholar
  11. 11.
    Klauk, H., Zschieschang, U., Halik, M.: Low voltage organic thin film transistors with large transconductance. J. Appl. Phys. 102(7), 0745141–074514-7 (2007)CrossRefGoogle Scholar
  12. 12.
    Raval, H.N., Tiwari, S.P., Navan, R.R., Mhaisalkar, S.G., Rao, V.R.: Solution processed bootstrapped organic inverters based on P3HT with a high-k gate dielectric material. IEEE Electron Device Lett. 30(5), 484–486 (2009)CrossRefGoogle Scholar
  13. 13.
    Spijkman, M., Smits, E.C.P., Blom, P.W.M., Leeuw, D., Bon Salnt Come, Y., Setayesh, S., Cantatore, E.: Increasing the noise margin in organic circuits using dual gate field effect transistors. Appl. Phys. Lett. 92(14), 143304 (1-3) (2008)Google Scholar

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© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringMadan Mohan Malaviya University of TechnologyGorakhpurIndia
  2. 2.Department of Electronics and Communication EngineeringDelhi Technological UniversityDelhiIndia

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