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Journal of Computational Electronics

, Volume 18, Issue 4, pp 1182–1191 | Cite as

Reduction of the kink effect in a SELBOX tunnel FET and its RF/analog performance

  • Puja GhoshEmail author
  • Brinda Bhowmick
Article

Abstract

The kink effect in a fully depleted silicon-on-insulator (SOI) tunnel field-effect transistor (TFET) is studied and compared with the results for a SOI metal–oxide–semiconductor field-effect transistor (MOSFET) using a model that is calibrated against experimental results available in literature. A technique for eliminating the kink effect is proposed. The structure with a small gap in the buried oxide, known as the selective buried oxide (SELBOX) structure, is capable of reducing the kink effect. The impact of the kink effect on the device performance for different gap positions, thicknesses, and buried oxide thicknesses is examined. A better current–voltage characteristic is obtained for a position of the gap near the source. The effect of varying the temperature and the presence of a uniform trap charge on the kink effect for the SOI TFET, SOI MOSFET, and SELBOX structures is also studied. Various electrical parameters such as the subthreshold swing and ION/IOFF ratio are investigated for the TFET in the presence and absence of uniform trap charge. Although the SELBOX structure can minimize the kink effect, it is still present for such devices with narrow and wider gaps. Therefore, the gap thickness is optimized based on technology computer-aided design (TCAD) simulations. Furthermore, radio frequency (RF)/analog performance parameters such as the transconductance (gm), cutoff frequency (ft), transconductance generation factor (TGF = gm/ID), transconductance frequency product, gain transconductance frequency product, and 1-dB compression point are investigated using TCAD simulations and compared between the SELBOX MOSFET and SELBOX TFET devices.

Keywords

TFET SOI SELBOX TGF TFP GTFP 

Notes

References

  1. 1.
    Choi, W.Y., Park, B.-G., Lee, J.D., Liu, T.-J.K.: Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28, 743–745 (2007)CrossRefGoogle Scholar
  2. 2.
    Gandhi, R., Chen, Z., Singh, N., Banerjee, K., Lee, S.: Vertical Si-nanowire n-type tunneling FETs with low subthreshold swing (650 mV/decade) at room temperature. IEEE Electron Device Lett. 32, 437–439 (2011)CrossRefGoogle Scholar
  3. 3.
    Krishnamohan, T., Kim, D., Raghunathan, S., Saraswat, K.: Double-gate strained-Ge heterostructure. Tunneling FET (TFET) with record high drive currents and < 60 mV/dec subthreshold slope. In: IEEE Technical Digest–International Electron Devices Meeting, pp. 1–3 (2008)Google Scholar
  4. 4.
    Verhulst, A.S., Vandenberghe, W.G., Maex, K., Groeseneken, G.: Tunnel field-effect transistor without gate–drain overlap. Appl. Phys. Lett. 91, 1–3 (2007)CrossRefGoogle Scholar
  5. 5.
    Le, S.T., Jannaty, P., Luo, X., Zaslavsky, A., Perea, D.E., Dayeh, S.A., Picraux, S.T.: Axial SiGe heteronanowire tunneling field-effect transistors. Nano Lett. 12, 5850–5855 (2012)CrossRefGoogle Scholar
  6. 6.
    Tsutsui, G., Saitoh, M., Nagumo, T., Hiramoto, T.: Impact of SOI thickness fluctuation on threshold voltage variation in ultra-thin body SOI MOSFETs. IEEE Trans. Nanotechnol. 4, 369–373 (2005)CrossRefGoogle Scholar
  7. 7.
    Chander, S., Bhowmick, B., Baishya, S.: Heterojunction fully depleted SOI-TFET with oxide/source overlap. Superlattices Microstruct. 86, 43–50 (2015)CrossRefGoogle Scholar
  8. 8.
    Lee, M.J., Choi, W.Y.: Analytical model of single-gate silicon-on-insulator (SOI) tunneling field-effect transistors (TFETs). Solid State Electron. 63, 110–114 (2011)CrossRefGoogle Scholar
  9. 9.
    Sen, J., Baishya, S., Bhowmick, B.: Optimisation and length scaling of raised drain buried oxide SOI tunnel FET. Electron. Lett. 49, 1031–1033 (2013)CrossRefGoogle Scholar
  10. 10.
    Narayanan, M.R., Al-Nashash, H., Pal, D., Chandra, M., Yasmine Hammamet, T.: Frequency response of MOS devices with SELBOX structure. Presented at 2012 16th IEEE Mediterranean Electrotechnical Conference, pp. 1099–1102 (2012)Google Scholar
  11. 11.
    Kuo, J.B., Lin, S.C.: Low-Voltage SOI CMOS VLSI Devices and Circuits. Wiley, New York (2001)Google Scholar
  12. 12.
    Narayanan, M., Al-Nashash, H., Mazhari, B., Pal, D. Chandra, M.: Analysis of kink reduction in SOI MOSFET using selective back oxide structure. Active Passive Electron. Compon. Article ID 565827, 1–9 (2012)Google Scholar
  13. 13.
    Chen, J., Solomon, R., Chan, T.Y., Ko, P.K., Hu, C.: Threshold voltage and C–V characteristics of SOI MOSFET’s related to Si film thickness variation on SIMOX wafers. IEEE Trans. Electron Devices 39, 2346–2353 (1992)CrossRefGoogle Scholar
  14. 14.
    Bernstein, K., Norman, J.: SOI Circuit Design Concepts. Kluwer, Dordrecht (2000)Google Scholar
  15. 15.
    Kim, S.W., Choi, W.Y., Sun, M.-C., Park, B.-G.: Investigation on the corner effect of L-shaped tunneling field-effect transistors and their fabrication method. J. Nanosci. Nanotechnol. 13, 6376–6381 (2013)CrossRefGoogle Scholar
  16. 16.
    Lu, K., Dong, Y., Yang, W., Guo, Y.: Body effects on the tuning RF performance of PD SOI technology using four-port network. IEEE Electron Device Lett. 39, 795–798 (2018)CrossRefGoogle Scholar
  17. 17.
    Kim, S.W., Choi, W.Y., Sun, M.-C., Kim, H.W., Park, B.-G.: Design guideline of Si-based L-shaped tunneling field-effect transistors. Jpn. J. Appl. Phys. 51, 06FE09 (2012)CrossRefGoogle Scholar
  18. 18.
    Fossum, G., Yang, J.-W., Trivedi, V.P.: Suppression of corner effects in triple-gate MOSFETs. IEEE Electron Device Lett. 24, 745 (2003)CrossRefGoogle Scholar
  19. 19.
    Goswami, R., Bhowmick, B.: Hetero-gate-dielectric gate-drain underlap nanoscale TFET with a δp + Si1–xGex layer at source-channel tunnel junction. Presented at CGCCEE 2014 International Conference on Green Computing Communication and Electrical Engineering, pp. 1–5Google Scholar
  20. 20.
    Dash, S., Jena, B., Kumari, P., Mishra, G. P.: An analytical nanowire tunnel FET (NW-TFET) model with high-k dielectric to improve the electrostatic performance. Presented at PCITC 2015 IEEE Power, Communication and Information Technology Conference, pp. 447–451. Bhubaneswar (2015)Google Scholar
  21. 21.
    Sentaurus Device User, Synopsys (2009)Google Scholar
  22. 22.
    Schenk, A.: Rigorous theory and simplified model of the band-to-band tunneling in silicon. Solid State Electron. 36, 19–34 (1993)CrossRefGoogle Scholar
  23. 23.
    Redwan, N.S., Chern, W., Hoyt, J.L., Antoniadis, D.A.: Trap assisted tunneling and its effect on subthreshold swing of tunnel FETs. IEEE Trans. Electron Devices 63, 4380–4387 (2016)CrossRefGoogle Scholar
  24. 24.
    Nguyen, B.-Y., Celler, G., Mazuré, C.: A review of SOI technology and its applications. J. Integr. Circuits Syst. 4, 51–54 (2009)Google Scholar
  25. 25.
    Biswas, A., Dan, S.S., Royer, C.L., Grabinski, W., Ionescu, A.M.: TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model. Micro Electron. Eng. 98, 334–337 (2012)CrossRefGoogle Scholar
  26. 26.
    Tsuchiya, T., Sato, Y., Tomizawa, M.: Three mechanisms determining short-channel effects in fully-depleted SOI MOSFETs. IEEE Trans. Electron Devices 45, 1116–1121 (1998)CrossRefGoogle Scholar
  27. 27.
    Narang, R., Saxena, M., Gupta, R.S., Gupta, M.: Impact of temperature variations on the device and circuit performance of tunnel FET: a simulation study. IEEE Trans. Nanotechnol. 12, 951–957 (2013)CrossRefGoogle Scholar
  28. 28.
    Ehteshamuddin, M., Alharbi, A.G., Loan, S.A.: Impact of interface traps on the BTBT-current in tunnel field effect transistors. Presented at 2018 5th International Conference on Electrical and Electronics Engineering, pp. 224–227 (2018)Google Scholar
  29. 29.
    Sharma, D., Vishvakarma, S.K.: Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET. Microelectron. J. 46, 731–739 (2015)CrossRefGoogle Scholar
  30. 30.
    Mohapatra, S.K., Pradhan, K.P., Artola, L., Sahu, P.K.: Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET. Mater. Sci. Semicond. Process. 31, 455–462 (2015)CrossRefGoogle Scholar
  31. 31.
    Barah, D., Singh, A.K., Bhowmick, B.: TFET on selective buried oxide (SELBOX) substrate with improved ION/IOFF ratio and reduced ambipolar current. Silicon (2018).  https://doi.org/10.1007/s12633-018-9894-0 CrossRefGoogle Scholar
  32. 32.
    Kranti, A., Armstrong, G.A.: Nonclassical channel design in MOSFETs for improving OTA gain-bandwidth trade-off. IEEE Trans. Circuits Syst. I Regul. Pap. 57, 3048–3054 (2010)MathSciNetCrossRefGoogle Scholar
  33. 33.
    Gautam, R., Saxena, M., Gupta, R.S., Gupta, M.: Effect of localised charges on nanoscale cylindrical surrounding gate MOSFET: analog performance and linearity analysis. Microelectron. Reliab. 52, 989–994 (2012)CrossRefGoogle Scholar
  34. 34.
    Rawat, A.S., Gupta, S.K.: Potential modeling and performance analysis of junction-less quadruple gate MOSFETs for analog and RF applications. Microelectron. J. 66, 89–102 (2017)CrossRefGoogle Scholar
  35. 35.
    Madan, J., Chaujar, R.: Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability. IEEE Trans. Device Mater. Reliab. 16, 227–234 (2016)CrossRefGoogle Scholar
  36. 36.
    Kumar, S.P., Agrawal, A., Chaujar, R., Gupta, R.S., Gupta, M.: Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor. Microelectron. Reliab. 51, 587–596 (2011)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringNational Institute of Technology SilcharSilcharIndia

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