Understanding the electrostatics of top-electrode vertical quantized Si nanowire metal–insulator–semiconductor (MIS) structures for future nanoelectronic applications

  • Subhrajit Sikdar
  • Basudev Nag Chowdhury
  • Sanatan ChattopadhyayEmail author


In this paper, a comprehensive analysis of the electrostatics of top-electrode vertically aligned quantized Si nanowire metal–insulator–semiconductor (MIS) structure is performed by formulating a self-consistent analytical model with simultaneous solution of Schrodinger and Poisson equations. The impact of high-k dielectrics on the electrostatic control of such quantized nanowire MIS devices is studied in detail. The electrostatic control is observed to degrade significantly for such high-k insulators with identical equivalent oxide thickness (EOT) due to the nonlinear dependence between dielectric constant and EOT in quantized nanowire MIS devices. The distribution of 3D confined charges along the nanowire is primarily governed by the generated quantum states which are a nonlinear function of the applied voltage. The electrostatic integrity of such device is investigated in terms of simultaneously maintaining the electrostatic control and reduction in carrier tunneling probability. In this context, the impact of several controlling parameters such as applied voltage, barrier height of the insulator/semiconductor junction, carrier effective mass of the insulator and nanowire diameter on tunneling probability is examined. The results suggest insulator effective mass (high-m*) to be the more significant parameter for maintaining electrostatic integrity than its dielectric constant (high-k) in quantized nanowire top-electrode MIS devices.


Si nanowire MIS structure High-k Electrostatic control Tunneling probability 



Mr. Subhrajit Sikdar thanks the University Grant Commission (UGC), Government of India, for funding the fellowship through University of Calcutta. The authors also thank the Center of Excellence (COE) for the Systems Biology and Biomedical Engineering, and Center for Research in Nanoscience and Nanotechnology (CRNN), University of Calcutta, for providing the necessary infrastructural support.


  1. 1.
    Soo, M.T., Cheong, K.Y., Noor, A.F.M.: Advances of SiC-based MOS capacitor hydrogen sensors for harsh environment applications. Sens. Actuators B Chem. 151, 39–55 (2010)CrossRefGoogle Scholar
  2. 2.
    Zhou, G., Wu, B., Liu, X., Li, P., Zhang, S., Sun, B., Zhou, A.: Two-bit memory and quantized storage phenomenon in conventional MOS structures with double-stacked Pt-NCs in an HfAlO matrix. Phys. Chem. Chem. Phys. 18, 6509–6514 (2016)CrossRefGoogle Scholar
  3. 3.
    Yasue, T., Kitamura, K., Watabe, T., Shimamoto, H., Kosugi, T., Watanabe, T., Aoyama, S., Monoi, M., Wei, Z., Kawahito, S.: A 1.7-in, 33-Mpixel, 120-frames/s CMOS image sensor with depletion-mode MOS capacitor-based 14-b two-stage cyclic A/D converters. IEEE Trans. Electron Devices 63, 153–161 (2016)CrossRefGoogle Scholar
  4. 4.
    Liu, A., Jones, R., Liao, L., Rubio, D.S., Rubin, D., Cohen, O., Nicolaescu, R., Paniccia, M.: A high-speed silicon optical modulator based on a metal–oxide–semiconductor capacitor. Nature 427, 615–618 (2004)CrossRefGoogle Scholar
  5. 5.
    Chatbouri, S., Troudi, M., Fargi, A., Kalboussi, A., Souifi, A.: The important contribution of photo-generated charges to the silicon nanocrystals photo-charging/discharging-response time at room temperature in MOS-photodetectors. Superlattices Microstruct. 94, 93–100 (2016)CrossRefGoogle Scholar
  6. 6.
    Tsai, P.C., Chen, W.R., Su, Y.K.: Enhanced ESD properties of GaN-based light-emitting diodes with various MOS capacitor designs. Superlattices Microstruct. 48, 23–30 (2010)CrossRefGoogle Scholar
  7. 7.
    Ho, W.-J., Liao, J.-J., Hou, Z.-F., Yeh, C.-W., Sue, R.-S.: High efficiency textured silicon solar cells based on an ITO/TiO2/Si MOS structure and biasing effects. Comput. Mater. Sci. 117, 596–601 (2016)CrossRefGoogle Scholar
  8. 8.
    Bhatia, D., Roy, S., Nawaz, S., Meena, R.S., Palkar, V.R.: Observation of temperature effect on electrical properties of novel Au/Bi0.7Dy0.3FeO3/ZnO/p-Si thin film MIS capacitor for MEMS applications. Microelectron. Eng. 168, 55–61 (2017)CrossRefGoogle Scholar
  9. 9.
    Chand, R., Han, D., Neethirajan, S., Kim, Y.-S.: Detection of protein kinase using an aptamer on a microchip integrated electrolyte-insulator-semiconductor sensor. Sens. Actuators B Chem. 248, 973–979 (2017)CrossRefGoogle Scholar
  10. 10.
    Kao, C.-H., Chang, C.-W., Chen, Y.T., Su, W.M., Lu, C.C., Lin, C.-Y., Chen, H.: Influence of NH3 plasma and Ti doping on pH-sensitive CeO2 electrolyte-insulator-semiconductor biosensors. Sci. Rep. 7, 1–9 (2017)CrossRefGoogle Scholar
  11. 11.
    Prakash, A., Maikap, S., Rahaman, S.Z., Majumdar, S., Manna, S., Ray, S.K.: Resistive switching memory characteristics of Ge/GeOx nanowires and evidence of oxygen ion migration. Nanoscale Res. Lett. 8, 220–230 (2013)CrossRefGoogle Scholar
  12. 12.
    Cho, S.Y., Yoo, H.-W., Kim, J.Y., Jung, W.-B., Jin, M.L., Kim, J.-S., Jeon, H.-J., Jung, H.-T.: High-resolution p-type metal oxide semiconductor nanowire array as an ultrasensitive sensor for volatile organic compounds. Nano Lett. 16, 4508–4515 (2016)CrossRefGoogle Scholar
  13. 13.
    Bae, J., Kim, H., Zhang, X.-M., Dang, C.H., Zhang, Y., Choi, Y.J., Nurmikko, A., Wang, Z.L.: Si nanowire metal–insulator–semiconductor photodetectors as efficient light harvesters. Nanotechnology 21, 095502.1–095502.5 (2010)CrossRefGoogle Scholar
  14. 14.
    Sikdar, S., Chowdhury, B.N., Ghosh, A., Chattopadhyay, S.: Analytical modeling to design the vertically aligned Si-nanowire metal-oxide-semiconductor photosensors for direct color sensing with high spectral resolution. Physica E 87, 44–50 (2017)CrossRefGoogle Scholar
  15. 15.
    Oener, S.Z., van Groep, J., Macco, B., Bronsveld, P.C.P., Kessels, W.M.M., Polman, A., Garnett, E.C.: Metal–insulator–semiconductor nanowire network solar cells. Nano Lett. 16, 3689–3695 (2016)CrossRefGoogle Scholar
  16. 16.
    Hobbs, R.G., Petkov, N., Holmes, J.D.: Semiconductor nanowire fabrication by bottom-up and top-down paradigms. Chem. Mater. 24, 1975–1991 (2012)CrossRefGoogle Scholar
  17. 17.
    Biswas, A., Bayer, I.S., Biris, A.S., Wang, T., Dervishi, E., Faupel, F.: Advances in top–down and bottom–up surface nanofabrication: techniques, applications & future prospects. Adv. Colloid Interface Sci. 170, 2–27 (2012)CrossRefGoogle Scholar
  18. 18.
    Ng, H.T., Han, J., Yamada, T., Nguyen, P., Chen, Y.P., Meyyappan, M.: Single crystal nanowire vertical surround-gate field-effect transistor. Nano Lett. 4, 1247–1252 (2004)CrossRefGoogle Scholar
  19. 19.
    Larrieu, G., Hanb, X.-L.: Vertical nanowire array-based field effect transistors for ultimate scaling. Nanoscale 5, 2437–2441 (2013)CrossRefGoogle Scholar
  20. 20.
    Hochbaum, A.I., Fan, R., He, R., Yang, P.: Controlled growth of Si nanowire arrays for device integration. Nano Lett. 5, 457–460 (2005)CrossRefGoogle Scholar
  21. 21.
    Mohan, P., Motohisa, J., Fukui, T.: Controlled growth of highly uniform, axial/radial direction-defined, individually addressable InP nanowire arrays. Nanotechnology 16, 2903–2907 (2005)CrossRefGoogle Scholar
  22. 22.
    Duc, T.-T.N., Gacusan, J., Kobayashi, N.P., Sanghadasa, M., Meyyappan, M., Oye, M.M.: Controlled growth of vertical ZnO nanowires on copper substrate. Appl. Phys. Lett. 102, 083105.1–083105.4 (2013)Google Scholar
  23. 23.
    Tomioka, K., Motohisa, J., Hara, S., Fukui, T.: Control of InAs nanowire growth directions on Si. Nano Lett. 8, 3475–3480 (2008)CrossRefGoogle Scholar
  24. 24.
    Zhao X, Lin J, Heidelberger C, Fitzgerald EA, del Alamo JA (2013) Vertical nanowire InGaAs MOSFETs fabricated by a top-down approach. IEEE Int Electron Devices Meet.
  25. 25.
    Tomioka, K., Yoshimura, M., Fukui, T.: A III-V nanowire channel on silicon for high-performance vertical transistors. Nature 488, 189–192 (2012)CrossRefGoogle Scholar
  26. 26.
    Hourdakis, E., Casanova, A., Larrieu, G., Nassiopoulou, A.G.: Three-dimensional vertical Si nanowire MOS capacitor model structure for the study of electrical versus geometrical Si nanowire characteristics. Solid State Electron. 143, 77–82 (2018)CrossRefGoogle Scholar
  27. 27.
    Fan, Wu, Qiao, Qiquan, Bahrami, Behzad, Chen, Ke, Pathak, Rajesh, Mabrouk, Sally, Tong, Yanhua, Li, Xiaoyi, Zhang, Tiansheng, Jian, Ronghua: Comparison of performance and optoelectronic processes in ZnO and TiO2 nanorod array-based hybrid solar cells. Appl. Surf. Sci. 456, 124–132 (2018)CrossRefGoogle Scholar
  28. 28.
    Yeo, Y.-C., King, T.-J., Hu, C.: MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations. IEEE Trans. Electron Devices 50, 1027–1035 (2003)CrossRefGoogle Scholar
  29. 29.
    Locquet, J.-P., Marchiori, C., Sousa, M., Fompeyrine, J., Seo, J.W.: High-K dielectrics for the gate stack. J. Appl. Phys. 100, 051610.1–051610.14 (2006)CrossRefGoogle Scholar
  30. 30.
    Rahman, A., Guo, J., Datta, S., Lundstrom, M.S.: Theory of ballistic nanotransistors. IEEE Trans. Electron Devices 50, 1853–1864 (2003)CrossRefGoogle Scholar
  31. 31.
    Canham, L.T.: Silicon quantum wire array fabrication by electrochemical and chemical dissolution of wafers. Appl. Phys. Lett. 57, 1046–1048 (1990)CrossRefGoogle Scholar
  32. 32.
    Neophytou, N., Paul, A., Lundstrom, M.S., Klimeck, G.: Bandstructure effects in silicon nanowire electron transport. IEEE Trans. Electron Devices 55, 1286–1297 (2008)CrossRefGoogle Scholar
  33. 33.
    Lo, S.-H., Buchanan, D., Taur, Y., Wang, W.: Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET’s. IEEE Electron Device Lett. 18, 209–211 (1997)CrossRefGoogle Scholar
  34. 34.
    Ochiai, M., Akita, M., Ohno, Y., Kishimoto, S., Maezawa, K., Mizutani, T.: AlGaN/GaN heterostructure metal-insulator-semiconductor high-electron-mobility transistors with Si3N4 gate insulator. Jpn. J. Appl. Phys. 42, 2278–2280 (2003)CrossRefGoogle Scholar
  35. 35.
    Ye, P.D., Wilk, G.D., Yang, B., Kwo, J., Chu, S.N.G., Nakahara, S., Gossmann, H.-J.L., Mannaerts, J.P., Hong, M., Ng, K.K., Bude, J.: GaAs metal–oxide–semiconductor field-effect transistor with nanometer-thin dielectric grown by atomic layer deposition. Appl. Phys. Lett. 83, 180–182 (2003)CrossRefGoogle Scholar
  36. 36.
    Rastogi, A., Desu, S.: Current conduction and dielectric behavior of high k-Y2O3 films integrated with Si using chemical vapor deposition as a gate dielectric for metal-oxide-semiconductor devices. J. Electroceram. 13, 121–127 (2004)CrossRefGoogle Scholar
  37. 37.
    Kang, L., Lee, B.H., Qi, W.-J., Jeon, Y., Nieh, R., Gopalan, S., Onishi, K., Lee, J.C.: Electrical characteristics of highly reliable ultrathin hafnium oxide gate dielectric. IEEE Electron Device Lett. 21, 181–183 (2000)CrossRefGoogle Scholar
  38. 38.
    Lee, B.H., Kang, L., Nieh, R., Qi, W.-J., Lee, J.C.: Thermal stability and electrical characteristics of ultrathin hafnium oxide gate dielectric reoxidized with rapid thermal annealing. Appl. Phys. Lett. 76, 1926–1928 (2000)CrossRefGoogle Scholar
  39. 39.
    Wu, Y., Yang, M., Chin, A., Chen, W., Kwei, C.: Electrical characteristics of high quality La2O3 gate dielectric with equivalent oxide thickness of 5 Å. IEEE Electron Device Lett. 21, 341–343 (2000)CrossRefGoogle Scholar
  40. 40.
    Kakushima, K., Tachi, K., Ahmet, P., Tsutsui, K., Sugii, N., Hattori, T., Iwai, H.: Advantage of further scaling in gate dielectrics below 0.5 nm of equivalent oxide thickness with La2O3 gate dielectrics. Microelectron. Reliab. 50, 790–793 (2010)CrossRefGoogle Scholar
  41. 41.
    Roy, K., Mukhopadhyay, S., Meimand, H.M.: Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE 91, 305–327 (2003)CrossRefGoogle Scholar
  42. 42.
    Bastard, G.: Superlattice band structure in the envelope-function approximation. Phys. Rev. B 24, 5693–5697 (1981)CrossRefGoogle Scholar
  43. 43.
    Yeo, Yee-Chia, King, Tsu-Jae, Chenming, Hu: Direct tunneling leakage current and scalability of alternative gate dielectrics. Appl. Phys. Lett. 81, 2091–2093 (2002)CrossRefGoogle Scholar
  44. 44.
    Yeo, Y.C., Lu, Q., Lee, W.C., King, T.-J., Hu, C., Wang, X., Guo, X., Ma, T.P.: Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric. IEEE Electron Device Lett. 21, 540–542 (2000)CrossRefGoogle Scholar
  45. 45.
    Hinkle, C.L., Fulton, C., Nemanich, R.J., Lucovsky, G.: A novel approach for determining the effective tunneling mass of electrons in HfO2 and other high-K alternative gate dielectrics for advanced CMOS devices. Microelectron. Eng. 72, 257–262 (2004)CrossRefGoogle Scholar
  46. 46.
    Monaghan, S., Hurley, P., Cherkaoui, K., Negara, M.A., Schenk, A.: Determination of electron effective mass and electron affinity in HfO2 using MOS and MOSFET structures. Solid-State Electron. 53, 438–444 (2009)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  • Subhrajit Sikdar
    • 1
  • Basudev Nag Chowdhury
    • 1
  • Sanatan Chattopadhyay
    • 1
    Email author
  1. 1.Department of Electronic ScienceUniversity of CalcuttaKolkataIndia

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