Advertisement

NAND flash memory device with ground plane in buried oxide for reduced short channel effects and improved data retention

  • Pooja Bohara
  • Santosh Kumar VishvakarmaEmail author
Article
  • 14 Downloads

Abstract

In this work, we investigate a promising technique for improving the performance of silicon-on-insulator (SOI) silicon-oxide-nitride-oxide-silicon (SONOS) NAND flash memory cells with ground plane in buried oxide (GPB). The physical phenomena that potentially degrade the performance of NAND flash memory cells at lower gate length are controlled by selection of an appropriate NAND flash device architecture. The various attributes of SONOS memory cells with GPB are compared with conventional SOI SONOS memory devices. It is shown that at the scaled gate length of 25 nm, a flash memory cell with GPB limits the short channel effects and achieves ~ 103 times higher memory speed. The short channel performance is evaluated by considering subthreshold slope (SS) and drain-induced barrier lowering (DIBL) parameters, which show significant improvement in SS along with relatively lower DIBL values at lower gate lengths in SONOS cells with GPB. The results highlight that a ~ 1.3 times wider memory window and ~ 2.4 times higher retention can be obtained over a period of 10 years in a SONOS GPB device in comparison to the SOI SONOS memory device. The present work provides guidelines to design highly dense flash memory devices while achieving improved reliability without altering the gate stack.

Keywords

Ground plane in buried oxide Silicon-oxide-nitride-oxide-silicon Short channel effects Silicon-on-insulator 

Notes

Acknowledgement

This work was supported by the Council of Scientific and Industrial Research (CSIR), Government of India, under Grant 22(0651)/14/EMR-II and Junior Research Fellowship Award to Pooja Bohara by University Grants Commission (UGC), Government of India, under Grant 4016/NET-JUNE 2013.

References

  1. 1.
    Takeuchi, K.: Scaling challenges of NAND flash memory and hybrid memory system with storage class memory and NAND flash memory. In: IEEE Custom Integrated Circuits Conference, pp. 1–6 (2013)Google Scholar
  2. 2.
    Georgiev, V.P., Markov, S., Vilà-Nadal, L., Busche, C., Cronin, L., Asenov, A.: Optimization and evaluation of variability in the programming window of a flash cell with molecular metal–oxide storage. IEEE Trans. Electron Devices 61(6), 2019–2026 (2014)CrossRefGoogle Scholar
  3. 3.
    Poliakov, P., Blomme, P., Pret, A.V., Corbalan, M.M., Gronheid, R., Verkest, D., Houdt, J.V., Dehaene, W.: Induced variability of cell-to-cell interference by line edge roughness in NAND flash arrays. IEEE Electron Device Lett. 33(2), 164–166 (2012)CrossRefGoogle Scholar
  4. 4.
    Saha, S.K.: Scaling considerations for sub-90 nm split-gate flash. IET Circuits Devices Syst. 2(1), 144–150 (2008)CrossRefGoogle Scholar
  5. 5.
    Gelpey, J., McCoys, S., Kontos, A., Godet, L., Hatem, C., Camms, D., Chan, J., Papasouliotis, G., Scheuer, J.: Ultra-shallow junction formation using flash annealing and advanced doping techniques. In: International Workshop on Junction Technology, pp. 82–86 (2008)Google Scholar
  6. 6.
    Shima, A., Ashihara, H., Mine, T., Goto, Y., Horiuchi, M., Wang, Y., Talwar, S., Hiraiwa, A.: Self-limiting laser thermal process for ultra-shallow junction formation of 50-nm gate CMOS. In: IEEE International Electron Devices Meeting, pp. 20.4.1–20.4.4 (2003)Google Scholar
  7. 7.
    Bang, T., Lee, B.H., Kim, C.K., Ahn, D.C., Jeon, S.B., Kang, M.H., Oh, J.S., Choi, Y.K.: Low-frequency noise characteristics in SONOS flash memory with vertically stacked nanowire FETs. IEEE Electron Device Lett. 38(1), 40–43 (2017)CrossRefGoogle Scholar
  8. 8.
    Choi, S.J., Moon, D.-I.I., Kim, S., Ahn, J.H., Lee, J.S., Kim, J.Y., Choi, Y.K.: Nonvolatile memory by all-around-gate junctionless transistor composed of silicon nanowire on bulk substrate. IEEE Electron Device Lett. 32(5), 602–604 (2011)CrossRefGoogle Scholar
  9. 9.
    Aldegunde, M., Martinez, A., Barker, J.R.: Study of discrete doping-induced variability in junctionless nanowire MOSFETs using dissipative quantum transport simulation. IEEE Trans. Electron Devices 33(2), 194–196 (2012)CrossRefGoogle Scholar
  10. 10.
    Choi, S.J., Moon, D.-I.I., Kim, S., Duarte, J.P., Choi, Y.K.: Sensitivity of threshold voltage to nanowire width variation in junctionless transistors. IEEE Electron Device Lett. 32(2), 125–127 (2011)CrossRefGoogle Scholar
  11. 11.
    Chang, S.J., Bawedin, M., Xiong, W., Lee, J.H., Cristoloveanu, S.: FinFlash with buried storage ONO layer for flash memory application. Solid State Electron. 98, 59–66 (2012)CrossRefGoogle Scholar
  12. 12.
    Jang, K.H., Jang, H.J., Park, J.K., Cho, W.J.: Self-amplified dual gate charge trap flash memory for low-voltage operation. IEEE Electron Device Lett. 34(6), 756–758 (2013)CrossRefGoogle Scholar
  13. 13.
    Choi, J.H., Yu, C.G., Park, J.T.: Nanowire width dependence of data retention and endurance characteristics in nanowire SONOS flash memory. Microelectron. Reliab. 64, 215–219 (2016)CrossRefGoogle Scholar
  14. 14.
    Micheloni, R. (ed.): 3D Flash Memories. Springer, Heidelberg (2016)Google Scholar
  15. 15.
    Micheloni, R., Crippa, L., Zambelli, C., Olivo, P.: Architectural and integration options for 3D NAND flash memories. Computers 6(3), 27 (2017)CrossRefGoogle Scholar
  16. 16.
    Jeong, M.K., Joe, S.M., Seo, C.S., Han, K.R., Choi, E., Park, S.K., Lee, J.H.: Analysis of random telegraph noise and low frequency noise properties in 3-D stacked NAND flash memory with tube-type poly-Si channel structure. In: Symposium on VLSI Technology (VLSI-Technology), Honolulu, HI, pp. 55–56 (2012)Google Scholar
  17. 17.
    Kim, S.Y., Park, J.K., Hwang, W.S., Lee, S.J., Lee, K.H., Pyi, S.H., Cho, B.J.: Dependence of grain size on the performance of a polysilicon channel TFT for 3D NAND Flash memory. J. Nanosci. Nanotechnol. 16, 5044–5048 (2016)CrossRefGoogle Scholar
  18. 18.
    Li, X., Huo, Z., Jin, L., Wang, Y., Liu, J., Jiang, D., Yang, X., Liu, M.: Investigation of charge loss mechanisms in 3D TANOS cylindrical junction-less charge trapping memory. In: IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1–3 (2014)Google Scholar
  19. 19.
    Yanagihara, Y., Miyaji, K., Takeuchi, K.: Control Gate Length, Spacing and Stacked Layer Number Design for 3D-Stackable NAND Flash Memory, pp. 1–4. IEEE International Memory Workshop, Milan (2012)Google Scholar
  20. 20.
    Jang, J., Kim, H.S., Cho, W., Cho, H., Kim, J., Shim, S.I., Younggoan Jeong, J.H., Son, B.K., Kim, D.W., Kihyun Shim, J.J., Lim, J.S., Kim, K.H., Yi, S.Y., Lim, J.Y., Chung, D., Moon, H.C., Hwang, S., Lee, J.W., Son, Y.H., Chung, U.I, Lee, W.S.: Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory. In: Symposium on VLSI Technology, Honolulu, pp. 192–193 (2009)Google Scholar
  21. 21.
    Hsiao, Y.H., Lue, H.T., Hsu, T.H., Hsieh, K.Y., Lu, C.Y.: A Critical Examination of 3D Stackable NAND Flash Memory Architectures by Simulation Study of the Scaling Capability, pp. 1–4. IEEE International Memory Workshop, Seoul (2010)Google Scholar
  22. 22.
    Yanagi, S., Nakakubo, A., Omura, Y.: Proposal of a partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET for deep sub-0.1-μm channel regime. IEEE Electron Device Lett. 22(6), 278–280 (2001)CrossRefGoogle Scholar
  23. 23.
    Beranger, C.F., Perreau, P., Denorme, S., Tosti, L., Andrieu, F., Weber, O., Monfray, S., Barnola, S., Arvet, C., Campidelli, Y., Haendler, S., Beneyton, R., Perrot, C., Buttet, C.D., Gros, P., Nguyen, L.P., Leverd, F., Gouraud, P., Abbate, F., Baron, F., Torres, A., Laviron, C., Pinzelli, L., Vetier, J., Borowiak, C., Margain, A., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.Y., Faynot, O., Skotnicki, T.: Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below. In: Proceedings of ESSCIRC, pp. 88–91 (2009)Google Scholar
  24. 24.
    Kumar, M.J., Siva, M.: The ground plane in buried oxide for controlling short-channel effects in nanoscale SOI MOSFETs. IEEE Trans. Electron Devices 55(6), 1554–1557 (2008)CrossRefGoogle Scholar
  25. 25.
    Yang, I.Y., Lochtefeld, A., Antoniadis, D.A.: Silicon-on-insulator-with-active-substrate (SOIAS) technology. In: IEEE International SOI Conference Proceedings, pp. 106–107 (1996)Google Scholar
  26. 26.
    Yang, I.Y., Vieri, C., Chandrakasan, A., Antoniadis, D.A.: Back-gated CMOS on SOIAS for dynamic threshold voltage control. IEEE Trans. Electron Devices 44(5), 822–831 (1997)CrossRefGoogle Scholar
  27. 27.
    Ocker, J., Slesazeck, S., Mikolajick, T., Buschbeck, S., Günther, S., Yurchuk, E., Hoffmann, R., Beyer, V.: On the voltage scaling potential of SONOS non-volatile memory transistors. In: European Solid State Device Research Conference (ESSDERC), Graz, pp. 118–121 (2015)Google Scholar
  28. 28.
    Wang, X., Kwong, D.L.: A novel high-κ SONOS memory using TaN/Al2O3/Ta2O5/HfO2/Si structure for fast speed and long retention operation. IEEE Trans. Electron Devices 53(1), 78–82 (2006)CrossRefGoogle Scholar
  29. 29.
    Wang, X., Liu, J., Bai, W., Kwong, D.L.: A novel MONOS-type nonvolatile memory using high-κ dielectrics for improved data retention and programming speed. IEEE Trans. Electron Devices 51(4), 597–602 (2004)CrossRefGoogle Scholar
  30. 30.
    Lee, G.H., Yang, H.J., Jung, S.W., Choi, E.S., Park, S.K., Song, Y.H.: Physical modeling of program and erase speeds of metal–oxide–nitride–oxide–silicon cells with three-dimensional gate-all-around architecture. Jpn. J. Appl. Phys. 53, 014201 (2014)CrossRefGoogle Scholar
  31. 31.
    Hsu, T.H., Lue, H.T., Lai, S.C., King, Y.C., Hsieh, K,Y., Liu, R., Lu, C.Y.: Reliability of planar and FinFET SONOS devices for NAND flash applications—field enhancement versus barrier engineering. In: International Symposium on VLSI Technology, Systems, and Applications, pp. 154–155 (2009)Google Scholar
  32. 32.
    Sentaurus TCAD Manuals Synopsys. Inc. Mountain view, CA (2016)Google Scholar
  33. 33.
    Lue, H.T., Wang, S.Y., Lai, E.K., Shih, Y.H., Lai, S.C., Yang, L.W., Chen, K.C., Joseph, K., Hsieh, K.Y., Rich, L., Lu, C.Y.: BE-SONOS: a bandgap engineered SONOS with excellent performance and reliability. In: IEEE International Electron Devices Meeting, pp 547–550 (2005)Google Scholar
  34. 34.
    Gupta, D., Vishvakarma, S.K.: Improved short-channel characteristics with long data retention time in extreme short-channel flash memory devices. IEEE Trans. Electron Devices 63(2), 668–674 (2016)CrossRefGoogle Scholar
  35. 35.
    Gupta, D., Vishvakarma, S.K.: Impact of LDD depth variations on the performance characteristics of SONOS NAND flash device. IEEE Trans. Device Mater. Reliab. 16(3), 298–303 (2016)CrossRefGoogle Scholar
  36. 36.
    Hsu, T.H., Lue, H.T., Hsieh, C.C., Lai, E.K., Lu, C.P., Hong, S.P., Wu. M.T., Hsu, F.H., Lien, N.Z., Hsieh, J.Y., Yang, L.W., Yang, T., Chen, K.C., Hsieh, K.Y., Liu, R., Lu, C.Y.: Study of sub-30 nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application. In: IEEE International Electron Devices Meeting, pp. 1–4 (2009)Google Scholar
  37. 37.
    Conde, A.O., Sánchez, F.J.G., Liou, J.J., Cerdeira, A., Estrada, M., Yue, Y.: A review of recent MOSFET threshold voltage extraction methods. Microelectron. Reliab. 42(4–5), 583–596 (2002)CrossRefGoogle Scholar
  38. 38.
    Colinge, J.-P.: Silicon-on-Insulator Technology: Materials to VLSI, 3rd edn. Springer, New York (2004)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Nanoscale Devices, VLSI Circuit and System Design Laboratory, Discipline of Electrical EngineeringIndian Institute of Technology IndoreSimrolIndia

Personalised recommendations