Journal of Computational Electronics

, Volume 16, Issue 2, pp 221–227 | Cite as

Improved device performance in a CNTFET using La\(_{2}\)O\(_{3}\) high-\(\kappa \) dielectrics

Article
First Online:

Abstract

The scaling of MOSFETs is an important and effective way for achieving high performance and low power consumption. One of the bottlenecks for scaling is the physical gate oxide thickness. This paper presents and evaluates a new method for scaling carbon nanotube field-effect transistors (CNTFETs) using \(\hbox {La}_{2}\hbox {O}_{3}\) as a new gate dielectric, which has excellent electrical properties. The proposed CNTFET is simulated using HSPICE. Some of the main digital and analog parameters such as current ratio, subthreshold swing (SS), transconductance, and intrinsic gain have been studied. The simulation results show that the proposed CNTFET outperforms present CNTFETs in terms of current ratio, transconductance, and intrinsic gain.

Keywords

Carbon nanotube field-effect transistor (CNTFET) High-\(\kappa \) dielectrics \(\hbox {La}_{2}\hbox {O}_{3}\) Transconductance 
This is a preview of subscription content, log in to check access.

References

  1. 1.
    Maitra, K., Khakifirooz, A., Kulkarni, P., Basker, V.S., Faltermeier, J., Jagannathan, H., Adhikari, H., Yeh, C.-C., Klymko, N.R., Saenger, K.: Aggressively scaled strained-silicon-on-insulator undoped-body high-/metal-gate nfinfets for high-performance logic applications. IEEE Electron Device Lett. 32, 713–715 (2011)CrossRefGoogle Scholar
  2. 2.
    Vogel, E.M., Ahmed, K.Z., Hornung, B., Henson, W.K., McLarty, P.K., Lucovsky, G., Hauser, J.R., Wortman, J.J.: Modeled tunnel currents for high dielectric constant dielectrics. IEEE Trans. Electron Devices 45, 1350–1355 (1998)CrossRefGoogle Scholar
  3. 3.
    Wu, M., Alivov, Y.I., Morkoc, H.: High-k dielectrics and advanced channel concepts for Si MOSFET. J. Mater. Sci. Mater. Electron. 19, 915–951 (2008)CrossRefGoogle Scholar
  4. 4.
    Dass, D., Prasher, R., Vaid, R.:Characterization of carbon nanotube field effect transistor using simulation approach. In: Conference on Physics of Semiconductor Devices, pp. 585–588. Springer, Berlin (2014)Google Scholar
  5. 5.
    Naderi, A.: Double gate graphene nanoribbon field effect transistor with electrically induced junctions for source and drain regions. J. Comput. Electron. 15, 347–357 (2016)CrossRefGoogle Scholar
  6. 6.
    Shashank, N., Singh, V., Taube, W.R., Nahar, R.K.: Role of interface charges on high-k based poly-Si and aetal gate nano-scale MOSFETs. J. Nano Electron. Phys. 3, 937–941 (2011)Google Scholar
  7. 7.
    Rouf, N.T., Deep, A.H., Binte Hassan, R., Khan, S.A., Hasan, M., Mominuzzaman, S.M.: Current–voltage characteristics of CNTFET considering non-ballistic conduction: effect of dielectric constant. In: 2014 9th IEEE International Conference on Nano/Micro Engineered and Molecular Systems (NEMS), pp. 256–259 (2014)Google Scholar
  8. 8.
    A Semiconductor Industry, National technology roadmap for semiconductors. SIA, San Jose (1997)Google Scholar
  9. 9.
    Liao, L., Duan, X.: Graphene-dielectric integration for graphene transistors. Mater. Sci. Eng. R Rep. 70, 354–370 (2010)CrossRefGoogle Scholar
  10. 10.
    Sasaki, H., Ono, M., Yoshitomi, T., Ohguro, T., Nakamura, S-i, Saito, M., Iwai, H.: 1.5 nm direct-tunneling gate oxide Si MOSFET’s. IEEE Trans. Electron Devices 43, 1233–1242 (1996)CrossRefGoogle Scholar
  11. 11.
    Swapna, P., Babu, K.K., Rambabu, B., Rao, Y.S.: Ambipolar CNTFET: basic characterization and effect of high dielectric material. In: 2011 International Conference on (NSTSI), pp. 1–4 (2011)Google Scholar
  12. 12.
    Owlia, H., Keshavarzi, P.: Investigation of the novel attributes of a double-gate graphene nanoribbon FET with AlN high-k dielectrics. Superlattices Microstruct. 75, 613–620 (2014)CrossRefGoogle Scholar
  13. 13.
    Naderi, A., Keshavarzi, P.: Novel carbon nanotube field effect transistor with graded double halo channel. Superlattices Microstruct. 51, 668–679 (2012)CrossRefGoogle Scholar
  14. 14.
    Feng, Q., Wang, Q., Xing, T., Li, Q., Hao, Y.: Electrical characteristics of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor using La2O3 gate dielectric. Sci. China Technol. Sci. 56, 629–632 (2013)CrossRefGoogle Scholar
  15. 15.
    Deng, J., Wong, H.S.P.: A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part I: model of the intrinsic channel region. IEEE Trans. Electron Devices 54, 3186–3194 (2007)CrossRefGoogle Scholar
  16. 16.
    Deng, J., Wong, H.S.P.: A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part II: full device model and circuit performance benchmarking. IEEE Trans. Electron Devices 54, 3195–3205 (2007)CrossRefGoogle Scholar
  17. 17.
    Chau, R., Datta, S., Doczy, M., Doyle, B., Kavalieros, J., Metz, M.: High-k metal-gate stack and its MOSFET characteristics. IEEE Electron Device Lett. 25, 408–410 (2004)CrossRefGoogle Scholar
  18. 18.
    Huang, A.P., Yang, Z.C., Chu, P.K.: Hafnium-based high-k gate dielectrics. In Conference on Advances in Solid State Circuits Technologie, p. 333 (2010)Google Scholar
  19. 19.
    Plummer, J.D., Griffin, P.B.: Material and process limits in silicon VLSI technology. In: Proceedings of the IEEE, vol. 89, pp. 240–258 (2001)Google Scholar
  20. 20.
    Robertson, J.: High dielectric constant gate oxides for metal oxide Si transistors. Rep. Prog. Phys. 69, 327–341 (2006)CrossRefGoogle Scholar
  21. 21.
    Ellis, K.A., Buhrman, R.A.: Time-dependent diffusivity of boron in silicon oxide and oxynitride. Appl. Phys. Lett. 74, 967–969 (1999)CrossRefGoogle Scholar
  22. 22.
    Kumar, K., Chou, A.I., Lin, C., Choudhury, P., Lee, J.C., Lowell, J.K.: Optimization of sub 3 nm gate dielectrics grown by rapid thermal oxidation in a nitric oxide ambient. Appl. Phys. Lett. 70, 384–386 (1997)CrossRefGoogle Scholar
  23. 23.
    Roy, P.K., Kizilyalli, I.C.: Stacked high-k gate dielectric for gigascale integration of metal-oxide-semiconductor technologies. Appl. Phys. Lett. 72, 2835 (1998)CrossRefGoogle Scholar
  24. 24.
    Liu, F.: Electrical characterization and modeling of advanced SOI materials and devices. Micro and nanotechnologies/Microelectronics. Universit’e Grenoble Alpes, (2015)Google Scholar
  25. 25.
    Zhang, Y., Smorchkova, I.P., Elsass, C.R., Keller, S., Ibbetson, J.P., Denbaars, S., Mishra, U.K., Singh, J.: Charge control and mobility in AlGaN/GaN transistors: experimental and theoretical studies. J. Appl. Phys. 87, 7981–7987 (2000)CrossRefGoogle Scholar
  26. 26.
    Wu, Y., Singh, M., Singh, J., Mishra, U.: Transport in metal-nitride heterostructure junctions-a self-consistent drift-diffusion-charge-control model Annual APS March Meeting 2003, March 3–7,(2003)Google Scholar
  27. 27.
    Singh, M., Singh, J., Mishra, U.: Current–voltage characteristics of polar heterostructure junctions. J. Appl. Phys. 91, 2989–2993 (2002)CrossRefGoogle Scholar
  28. 28.
    Gummel, H.K., Poon, H.C.: An integral charge control model of bipolar transistors. Bell Syst. Tech. J. 49, 827–852 (1970)CrossRefGoogle Scholar
  29. 29.
    Bahari, A., Khorshidi, Z.: High-k gate dielectric: amorphous Ta/La2o3 films grown on Si at low pressure. Surf. Rev. Lett. 21, 1450080 (2014)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2017

Authors and Affiliations

  1. 1.ACECR Institute of Higher EducationIsfahanIran
  2. 2.Academic Center for Education, Culture and Research (ACECR)Isfahan University of Technology (IUT) BranchIsfahanIran

Personalised recommendations