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Journal of Computational Electronics

, Volume 16, Issue 2, pp 459–472 | Cite as

Novel 8-bit reversible full adder/subtractor using a QCA reversible gate

  • Moein Kianpour
  • Reza Sabbaghi-NadooshanEmail author
Article

Abstract

Conventional digital circuits consume a considerable amount of energy. If bits of information remain during logical operations, power consumption decreases considerably because the data bits in reversible computations are not lost. The types of reversible gate used in quantum computations are quantum-dot cellular automata (QCA), nuclear magnetic resonance, and optical computations. QCA systems offer low power consumption, high density, section regularity and support new devices designed for nanotechnology. A QCA-based reversible gate has minimal delay, complexity and considering the potential quality of a QCA pipeline, computes at maximum speed. The present study designed a novel \(3 \times 3\) reversible gate that is universal and testable. A reversible logic gate is also designed based on the majority gate in the QCA and as a QCA reversible (QR) gate. A new 8-bit reversible full adder/subtractor based on the QR gate in QCA with a minimum number of cells and area combines both designs for implementation of a reversible full adder/subtractor in QCA. The performance of these gates was compared with testable Fredkin and Toffoli gates and improved performance of logic functions in terms of complexity and delay over those of the Fredkin and Toffoli gates.

Keywords

Adder/subtractor Defect Fault tolerant Majority gate Quantum-dot cellular automata (QCA) Reversible gate 

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Copyright information

© Springer Science+Business Media New York 2017

Authors and Affiliations

  1. 1.Young Researchers and Elite ClubIslamic Azad University, Central Tehran BranchTehranIran
  2. 2.Electrical Engineering DepartmentIslamic Azad University, Central Tehran BranchPounakIran

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