# Impact of phonon scattering in Si/GaAs/InGaAs nanowires and FinFets: a NEGF perspective

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## Abstract

This paper reviews our previous theoretical studies and gives further insight into phonon scattering in 3D small nanotransistors using non-equilibrium Green function methodology. The focus is on very small gate-all-around nanowires with Si, GaAs or InGaAs cores. We have calculated phonon-limited mobility and transfer characteristics for a variety of cross-sections at low and high drain bias. The nanowire cross-sectional area is shown to have a significant impact on the phonon-limited mobility and on the current reduction. In a study of narrow Si nanowires we have examined the spatially resolved power dissipation and the validity of Joule’s law. Our results show that only a fraction of the power is dissipated inside the drain region even for a relatively large simulated length extension (approximately 30 nm). When considering large source regions in the simulation domain, at low gate bias, a slight cooling of the source is observed. We have also studied the impact of the real part of phonon scattering self-energy on a narrow nanowire transistor. This real part is usually neglected in nanotransistor simulation, whereas we compute its impact on current–voltage characteristic and mobility. At low gate bias, the imaginary part strongly underestimated the current and the mobility by 50 %. At high gate bias, the two mobilities are similar and the effect on the current is negligible.

## Keywords

Silicon and III–V nanowire field effect transistors Non-equilibrium Green’s functions Electron–phonon scattering self-energies Phonon-limited mobility Local power dissipation## 1 Introduction

Three-dimensional field effect transistor structures, such as nanowires and FinFETs, have been extensively investigated. These structures provide a protection against short channel effects and excellent electrostatic integrity [1, 2, 3, 4].^{1} Their theoretical calculated subthreshold slope is almost 60 mV/dec for a well-balanced structure. Indeed, FinFET structures of approximately 40-nm channel length have been in production for several years. Understanding the miniaturization potential of these devices is of both economic and research importance.

Semiclassical simulation transport methodologies, such as drift diffusion, lose their predictability in the nanometer realm due to the wave nature of the electron. However, the charge integrity of MOSFET transistors seems to brush out some quantum effects. This happens when the effect of tunneling and confinement is negligible. Hence quasi-classical methodologies are still applicable at nanometer dimensions. Of course continuous calibration for each particular dimension is still required in order to accurately predict current–voltage characteristics. However, for transistors around tens of nanometers the quantum effect becomes so severe that solely quantum mechanical simulations can provide a reliable description of transport. For silicon devices with cross-sections under \(16\,\hbox {nm}^{2}\), confinement becomes important and therefore modeling the transport through sub-bands is strongly recommended. It appears that small gate length (under 10 nm) devices should be ballistic and of course this is true if the cross-section is much larger than \(16\,\hbox {nm}^{2}\) [5], but when the cross-section becomes smaller, the effective phonon coupling increases inversely proportional to the cross-section [6]. The physical reason is the strong localization of the electron wave function of the channel cross-section. This is reflected through the form factors [5, 7] that appear in the calculation of the electron–phonon scattering self-energies in the mode description. They depend on the inverse of the area of the cross-section and are the main reason for this decrease of phonon-limited mobility [6]. Therefore, narrow wires should have decreased phonon-limited mobility. This fact has been found out using a variety of theoretical models [8, 9] and has also been confirmed experimentally [10]. Of course, for small device cross-sections, interface scattering plays a very important role, as the volume/area ratio is small. However, here we will concentrate on the phonon scattering mechanism. Electron–electron scattering, surface roughness and photon emission have not been considered. However, their overall effect is negligible because they are elastic processes, which do not change the energy relaxation.

It is customary to only consider the imaginary part of the self-energy in device simulation. Only a handful of authors consider full self-energy [11, 12, 13, 14] as the calculation of the real part (or the renormalization of the levels due to electron phonon scattering) needs the computation of the Hilbert transform [15], which is very time-consuming. In addition, the conservation of the density of states requires the real as well as the imaginary part of the self-energy [17]. This is a consequence of the Kramers–Kronig relationship [16] or causality conditions (details in the “Appendix”). The neglect of the real part produces an underestimate of the electron density in the channel of the transistor; this fact has been pointed out by A. Svizhenko [12]. Similar effects have been observed by other authors [11, 13]. Ignoring the real part produces an underestimate of mobility at low inversion charges [14].

Another important issue is power dissipation in ultra-high-scale 3D integration [18, 19, 20]. Miniaturization compresses a huge number of devices into a small region and, when combined with the heat partially trapped inside the channel of a 3D MOSFET, makes heat release a difficult enterprise. Heat becomes trapped because an oxide material, which has a very low thermal conductivity, surrounds the channel. At device level, it is important to know where heat is dissipated, i.e., drain–channel interface or deep inside the drain. For narrow devices this is a complex issue as it depends on particular inelastic phonon energies and coupling constants and on the number of states available locally or the empty local density of states, which is broadened due to scattering and is dependent on the local potential. All this occurs under highly non-equilibrium conditions for shorter channel lengths. In order to capture these phenomena a non-equilibrium quantum description of transport is required. Datta et al. [21, 22] use a NEGF formalism in order to calculate the local power dissipation in a double-barrier resonant tunneling device. In those papers a good description of energy transfer and conservation laws in the NEGF formalism is presented. Mahan’s report [23] goes deeper into the conservation laws. Recently [24], we have calculated the local power using the NEGF formalism for Si GAA (gate-all-around) nanowire transistors. The calculation of local power is quite sensitive, as one needs to subtract two large terms in order to calculate the power dissipation (see Sect. 3). This means that the calculation of the local current spectra needs to be done quite accurately to ensure that the local current conservation is fulfilled with a relative error in the current of \(10^{-3}-10^{-4}\). This implies that many Born iterations are required making the calculation computationally expensive.

The improvement in the quality of III–V materials and their interfaces make the fabrication of small III–V transistors a real possibility [25]. The fact that these materials have direct band gap and high mobility makes them attractive for optoelectronic and digital applications. In this work we investigate ultra-scaled nanowire GAA transistors made of GaAs and InGaAs core. We compute the phonon-limited mobility and the impact of the scattering on the drain current.

The whole paper is divided into four sections. First we explore the effect of scattering in Si GAA nanowire transistors. The phonon-limited mobility and the current reduction due to electron phonon scattering are calculated for a variety of cross-sections. The impact of the real part of phonon scattering self-energies on the current and on the mobility in a narrow Si nanowire transistor has been quantified in section two. A complementary “Appendix” to section two discusses more technically some theoretical issues associated with causality, locality and the real part of the self-energy. In section three, the local power dissipation in a nanowire transistor is computed. The effect of the source region enlargement on the distribution of the carrier energy is also studied. Two different cross-sections are considered \((2.2\times 2.2\,\hbox {nm}^{2}, 3.6\times 3.6\,\hbox {nm}^{2})\). Different combinations of source, channel and drain length are explored.

Finally, in section four, the effect of scattering in GaAs and InGaAs (GAA) nanowire transistors is investigated. For two cross-sections (\(2.2\times 2.2\,\hbox {nm}^{2}\) and \(4.2\times 4.2\,\hbox {nm}^{2})\), the effect of confinement, reduction in the current due to electron–phonon scattering and phonon-limited mobility are discussed.

## 2 Electron–phonon scattering in GAA Si nanowires (low and high drain bias)

In this work, the electron is described using an effective mass approximation [6, 26, 27] and a mean field approximation. However, the masses are extracted from tight-binding calculations. Our model used an anisotropic mass tensor [4] and coupled mode space approach, in order to reduce computational time. The phonons are assumed to be in equilibrium, and the electron phonon scattering parameters are from reference [7], which has been shown to be a good approximation for confined structures. Acoustic and f-g-intervalley and intravalley phonon scattering mechanisms have been included. Unless otherwise specified, a gate-all-around (GAA) nanowire field effect transistor structure is considered. The channel is usually assumed to be undoped, and the n-type source and drain region are doped by \(10^{20}\,\hbox {cm}^{-3}\).

*x*-axis. The \(F_{m,\nu 1}^{n,\nu } \left( x \right) \) are the form factors given by:

*x*-location. The integration is over the whole cross-section. These form factors are proportional to the inverse of the cross-sectional area. Note that wave functions are normalized in the cross-sectional area. Figure 1 shows a slight decrease in mobility as the inversion charge increases, and this results from increasing intersub-band scattering at high fields [4]. It is worth pointing out that our results are in agreement with previous works [7, 28, 29, 30, 31] using different physical models. The agreement of our results with full-band method (tight-binding) is a consequence of the similarity of the density of states between the confined phonons and bulk phonons. This has been pointed out in a previous paper [4].

Another important aspect is the impact of phonon scattering in the electron current at high drain bias. This impact is measured by the ballisticity coefficient defined by \(100 \times (I_{\mathrm{scatt}}/I_{\mathrm{bal}})\) and by the percentage of the current reduction due to scattering, \(100*(I_{\mathrm{bal}}-I_{\mathrm{scatt}})/I_{\mathrm{bal}}\). The current reduction for the \(2.2\times 2.2\,\hbox {nm}^{2}\) cross-section as a function of the channel length is shown in Fig. 2. The current reduction considering only scattering in the channel is also shown for comparison. As expected as the channel increases, the effect of scattering increases becoming 85 % for 40 nm channel length. An important finding is that the impact of scattering for the 6 nm channel length small device is larger than 50 %. For the device of \(6.2\times 6.2\,\hbox {nm}^{2}\) at 6 nm channel length the current reduction is still substantial and is equal to 32 %, and the corresponding value for a 40 nm channel is 50 %.

We have demonstrated that phonon scattering is certainly non-negligible for *small* nanowire transistors. In addition the reduction in the nanowire cross-section makes the impact of scattering more severe.

## 3 Impact of the real part of the phonon scattering self-energies on silicon nanowires

A violation of causality or more general sum rules [32] can be associated with a breakdown of charge conservation [33] or other conservations laws. This is shown in the work of Friedel [34].

From a device point of view the lack of conservation of density states (DOS) and the underestimation of charge density can prevent the accurate determination of electron current. However, the real part of the self-energy also produces a negative local shift in the electron energy that when combined with the enforcement of charge neutrality (Poisson’s equation) produces effects in the current and mobility which are difficult to predict without the help of calculations. Technical details of causality and locality issues with self-energies are described in “Appendix.”

In summary, we have studied the impact of the real part of the self-energy on the current–voltage characteristic and on the mobility of a narrow Si GAA nanowire transistor. It has also been shown that the same behavior follows for a gated nanowire, so the effect is not strongly related to the source and drain regions. In general, we have confirmed that the neglect of the real part of the self-energy underestimated the electron density in the channel but this effect tends to disappear as the channel charge increases. This is due to the increasing impact of the channel charge in the channel electrostatic, which modifies the source–drain barrier.

## 4 Power dissipation in silicon nanowire transistors

As mentioned in the introduction, electrons in small transistors experience large applied bias within a distance of a few nanometers. A drain bias, as large as 1 V, is expected to be applied in these devices. This large change in electron potential energy leaves strong non-equilibrium electron distribution inside devices. In small cross-sections confinement and a reduced density of states make the selection of final energy states more difficult and also the relaxation of hot electrons. The fact that optical phonons in Si have an average energy of less than 100 meV implies that several phonon processes are needed to cool down a 0.4 eV hot electron. All the above effects decrease energy relaxation; however, in small cross-sections, the effective electron–phonon coupling is largely due to the form factor increasing [5], and this consequently increases energy relaxation. This interplay between different factors makes electron relaxation in nanotransistors a complex phenomena. Usually the Joule power relation *I* * *V*(*r*) [37] is used to estimate local energy dissipation; however, for very small transistors a more detailed analysis is required.

In this section a study of local power dissipation in a Si GAA nanowire transistor will be carried out. We use the same NEGF methodology, effective mass Hamiltonian and phonon scattering mechanism as in the previous sections.

As mentioned before we have assumed that the phonons are in equilibrium (300 K). It is known that the inclusion of non-equilibrium phonons results in a decrease of the current. However, the modeling of non-equilibrium phonons is a difficult task for small nanowires. Recent calculations of self-heating using atomistic phonons show a decrease in the current [36].

*J*(

*r*,

*e*) is the local electron current for energy

*e*. The local power transfer by the electron to the lattice is given by:

*I**

*V*. The first term in the RHS of (6) is the change in the “kinetic energy” current of the electron ensemble, if this kinetic energy current does not change it means that the electron system is following the bending of the potential and therefore not increasing the electron mean energy relative to the conduction band minima, i.e., no hot electron phenomena. In this case the electron system or more specifically the electrons taking part in the current are in equilibrium with the local potential. On the other hand a large change in kinetic current implies the heating or cooling of the electron system. Using Eqs. 11b and 12b in the appendix, we can obtain the detailed balance equation [22, 23]:

We have simulated a variety of source, channel and drain lengths in order to see the role of different device regions in power dissipation or energy transfer between the electron and phonon systems. Two different cross-sections have been investigated: a \(2.2\times 2.2\,\hbox {nm}^{2}\) and a \(3.6\times 3.6\,\hbox {nm}^{2}\).

First we concentrated on high gate bias for which power dissipation is relevant, and finally, we will present some effects at low gate bias, such as the cooling of the source, which is related to the Peltier effects [22].

Figure 10a, b shows the current spectra and power per unit length in the device with the larger cross-section. In this case dissipation is not as strong as in the case of the smaller cross-section, as it was expected. The mean energy of the electron current only drops 50 meV at the end of the drain, making the electron system very far from equilibrium inside the device. The position shifting between the maxima of the total and Joule power density is equal to (21.4–16.4) nm = 5 nm. The maximum values of the total and Joule power density by unit length are \(1.22\times 10^{-6}\) and \(4.04\times 10^{-8}\) W/nm. It is worth noting that the ratio between the two values is two orders of magnitude. As mentioned before, the reason for this large ratio when compared to the corresponding value of the small cross-sectional device is the large phonon scattering rate in the small cross-sectional device. The corresponding integrated total and Joule power through the whole device is \(6.3538\times 10^{-7}\) and \(3.2667\times 10^{-6}\) W/nm, respectively. In order to further explore relaxation in the drain region, devices with 10-/6-/64 nm source/channel/drain regions were simulated.

Figure 11 shows the current spectra for the small and large cross-sections, respectively. The average current energy flattens at the drain end, showing that equilibrium has been reached. However, this is not the case for the large cross-sectional device. The average current energy for the large cross-sectional device is still changing at the contact. The total power dissipated inside the device is 56 % of the Joule power. It is important to highlight that even for a relatively long drain region (65 nm), the hot electrons in the \(3.6\times 3.6\,\hbox {nm}^{2}\) device leave the drain without relaxation.

The value of the total and Joule reductions integrated through the whole simulated device length is summarized in Table 1 at \(V_\mathrm{G}=0.9\) V. In what follows, we highlight and discuss the relevant issues for every individual configuration.

Current reduction and percentage of joule power dissipated in different dimension devices

Source/channel/ drain (nm) | Cross-section \((\hbox {nm}^{2})\) | \(\hbox {P}_{T}/\hbox {P}_{J}\) (%) | Current reduction (%) |
---|---|---|---|

10/6/24 | \(2.2\times 2.2\) | 50 | 50 |

10/6/24 | \(3.6\times 3.6\) | 19 | 30 |

24/6/10 | \(2.2\times 2.2\) | 26 | 57 |

24/6/10 | \(3.6\times 3.6\) | 11 | 22 |

10/6/64 | \(2.2\times 2.2\) | 92 | 63 |

10/6/64 | \(3.6\times 3.6\) | 56 | 38 |

10/40/30 | \(2.2\times 2.2\) | 73 | 82 |

10/40/30 | \(3.6\times 3.6\) | 36 | 63 |

Longer source devices with 24-/6-/10 nm long source/channel/drain regions and \(2.2\times 2.2\, \hbox {nm}^{2}\) and \(3.6\times 3.6\hbox { nm}^{2}\) cross-section have been studied. Figure 12 shows the current spectra and the local power at low gate bias (\(V_\mathrm{G}=0.4\) V) in the small cross-sectional device. In this case the gate barrier energy is around 250 meV; source electrons surmounting the barrier through phonon absorption cool the source of the transistor. The upper panel of Fig. 12 shows that the average current energy in the drain is larger than the drain indicating a net cooling of the lattice. The integrated power inside the whole simulated device region extracted from Fig. 8 is negative, as the positive power dissipated in the drain is unable to compensate the cooling of the source. The Joule power and integrated power are \(1.0349\times 10^{-10}\) and \(-2.2232\times 10^{-11}\) W, but the total power integrated, including the device and its surrounding equilibrium regions, is positive and equals the Joule power as expected. This is similar to what happens at the interface of regions with different Peltier coefficients [22]. This negative local power occurs at very low gate bias. At high gate bias, the source cooling is very small as compared to the power dissipated in the drain, even for short drain extensions. At \(V_\mathrm{G}=0.9\) V, the joule and total powers are \(6.8285\times 10^{-7}\) W and \(1.8411\times 10^{-7}\) W, which results in only 26 % of the joule power dissipated inside the device. As the length of these devices is similar to the 10-/6-/24-nm device a comparison between the relaxation in the source and drain can be established.

Table 1 presents the current reduction and the percentage of Joule power (i.e., \(100\times P_\mathrm{T}/P_\mathrm{J}\), where \(P_\mathrm{T}\) is the power dissipated inside the device given by the integration over the whole device of the RHS of Eq. 6 or 7 and \(P_\mathrm{J}\) is the integration of the second term of Eq. 6) dissipated inside the device for different combinations of source/channel/drain dimensions.

Two features stand out: (i) Current reduction is mainly related to the channel length and in the small/large cross-section is approximately equal to 55/30 % on average for 6-nm channel length, (ii) total power dissipation is mostly related to the drain size, but it also increases with channel length. Devices with 10/40/30 and 10/6/64 have the same channel+drain length; however, the 64 nm drain device has a 20/37 % large power dissipation than the 30 nm drain in the small/large cross-section, respectively.

In this section local power dissipation through a narrow GAA nanowire transistor has been extracted for two different cross-sections. The electron system in the smaller cross-sectional transistor requires more than 60 nm to release its energy at the drain. For the large cross-sectional device more than 80 nm would be needed. This is an important finding as it means that most of the transistor’s power will be dissipated outside its active region and deep into the drain–contact interface. This is true for relatively large cross-sections but as the transistor’s cross-section shrinks, the power dissipated close to the channel–drain interface increases. It is worth noting that interface roughness and impurity scattering are elastic mechanisms and do not contribute to power dissipation. We have used bulk phonons, but our previous work suggests than even if this is a crude approximation for very small cross-sections, the phonon density of states for confined phonons is still concentrated around the bulk phonon energies see ref. [4]. Finally, we have observed as pointed out by other authors [21, 22] that a cooling of the lattice occurs in the source region at low gate bias.

## 5 GaAs and InGaAs nanowire field effect transistors

In this section, III–V (GaAs [100] and InGaAs [100]) n-channel nanowire field effect transistors (NWFETs) are discussed. III–V nanowires are under consideration for use in NWFETs because of their high mobility compared to Si. NWFETs of cross-sections \(2.2\times 2.2\,\hbox {nm}^{2}\) and \(4.2\times 4.2\,\hbox {nm}^{2}\) and channel length 6 nm have been simulated. The source and drain are 15 nm long and are doped at \(10^{20}\,\hbox {cm}^{-3}\). The channel is undoped. The structure of the NWFETs is given in Fig. 13. We have calculated the transfer characteristic for a drain bias of 0.6 V and extracted the current reduction. In addition, we have extracted the mobility using the methodology outlined in Sect. 3. The Hamiltonian has been written in the effective mass approximation; the masses are extracted from tight-binding calculations [38]. These masses calculated from tight-binding have been extracted as a function of the cross-section. The valleys are assumed to be isotropic.

Scattering of elastic acoustic phonons, optical intervalley (\(\Gamma -L, L-X, \Gamma -X, L-L, X-X\)), intravalley and polar optical (intravalley) phonons (POP) have been considered. In GaAs and InGaAs, polar optical phonon scattering is the dominant scattering mechanism, followed by \(\Gamma -L\) intervalley scattering. The polar phonon scattering self-energy has been considered to be local [39]. This approximation is made here as the implementation of non-local self-energies will render the use of the recursive algorithm invalid. The scattering parameters have been taken from [40].

*L*and

*X*. For the cross-sections of the devices simulated in this paper, there is strong confinement, which in the \(2.2\times 2.2\,\hbox {nm}^{2}\) cross-sectional devices causes the low mass \(\Gamma \)-valley to become elevated in energy [41]. This produces low current and mobility in the \(2.2\times 2.2\,\hbox { nm}^{2}\) devices.

*L*then

*X*.

*L*and

*X*-valleys contributing to the current. Figure 18 shows the \(I_\mathrm{D}-V_\mathrm{G}\) characteristics for the \(4.2\times 4.2\,\hbox {nm}^{2}\) cross-sectional, 6-nm channel devices at high drain bias. Due to the lower effective masses for the larger cross-sectional device, the current for the GaAs and InGaAs core devices is now closer.

The \(I_\mathrm{D}-V_\mathrm{G}\) characteristics for each valley in the \(2.2\times 2.2\,\hbox {nm}^{2}\) cross-sectional, GaAs core NWFET are shown in Fig. 19. The high mass *L*- and the *X*-valley provide the largest contribution to the transport; there is little current in the low mass \({\Gamma }\)-valley. For the equivalent InGaAs NWFET, the majority of the current is in the *L*-valley, with little current in the \({\Gamma }\) and *X*-valleys.

## 6 Conclusion

We have demonstrated that the effective mass approximation, in combination with the NEGF formalism, is a powerful tool in exploring the trend of different phenomena in small transistors. Quantum effects are described with the simplest approximation, and therefore, the technique is very efficient computationally. However, the masses and other parameters need to be renormalized (calibrated) using more sophisticated physical models such as density functional theory or tight-binding. In principle, non-parabolicity can be considered by introducing adiabatically energy-dependent masses. The inclusion of phonon scattering introduces a heavy computational burden as it adds a new self-consistent cycle. However, as we used local self-energies for scattering, the recursive algorithm can be still used and lightens the computational burden. For polar phonon scattering, the use of local self-energies is a more questionable approximation but it makes the computation possible. The use of different approximations for non-local phonons has been briefly studied in Ref [42]. Recently, a promising new methodology that conserves the current has been suggested [43, 44], but it has not been considered in this work.

The impact of scattering, as a function of the cross-section and channel length, on the current and mobility has been thoroughly investigated for different materials. We found that the main increase of scattering with decreasing cross-sections comes from the proportionality of the scattering rate to the cross-sectional area. The impact of the real part of the self-energy on the current voltage characteristic and mobility has also been computed, yielding a 50 % drain current increase at low gate bias, and is negligible at high gate bias. The mobility follows a similar trend. Power dissipation, spatially resolved, has been studied in a combination of source, channel and drain dimensions and for two different cross-sections. Hot electrons entering the drain need at least a 60 nm drain length to thermalize for a \(2.2\times 2.2\,\hbox {nm}^{2}\) cross-sectional device at a 0.4-V drain bias. This is for a short 6 nm gate length device. For large channel lengths, electrons start to thermalize in the channel and consequently require less drain length to reach equilibrium. However, electron energy relaxation becomes slower for large cross-sectional devices. This helps with power dissipation, as most of the power will be delivered at the drain–contact interface, which is not surrounded by an oxide material.

## Footnotes

- 1.
See http://www.itrs.net/for “International Technology Roadmap for Semiconductors.”

## Notes

### Acknowledgments

This work was supported by EPSRC under Career Acceleration Fellowship Grant No. EP/I004084/2: Quantum Simulations of Future Solid-State Transistors of A. Martinez.

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