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Journal of Computational Electronics

, Volume 14, Issue 3, pp 661–668 | Cite as

A novel high performance junctionless FETs with saddle-gate

  • Xiaoshi JinEmail author
  • Meile Wu
  • Xi Liu
  • Rongyan Chuai
  • Hyuck-In Kwon
  • Jung-Hee Lee
  • Jong-Ho Lee
Article

Abstract

In this paper, a novel junctionless field effect transistors (JL FETs) with a saddle-gate structure has been proposed, and the I–V characteristics has been extensively studied by TCAD device simulation. The performance comparison between saddle-gate JL FETs and conventional triple-gate JL FETs has also been performed. The influence of gate dielectric on device property has also been investigated. A scheme of design optimization of saddle-gate JL FETs has also been proposed.

Keywords

Saddle-gate Junctionless Field effect transistors Design optimization 

Notes

Acknowledgments

This work is supported by the Fund of Liaoning Province Education Department No. L2012028, No. L2013045, the fund of the ministry of education of China, and the National Natural Science Foundation of China No. 61372019.

References

  1. 1.
    Colinge, J.-P., Lee, C.-W., Afzalian, A., et al.: Nanowire transistors without junctions. Nat. Nanotechnol. 5(3), 225–229 (2010)CrossRefGoogle Scholar
  2. 2.
    Munteanu, D., Autran, J.-L.: 3-D Numerical simulation of bipolar amplification in junctionless double-gate MOSFETs under heavy-ion irradiation. IEEE Trans. Nucl. Sci. 59(4), 773–780 (2012)CrossRefGoogle Scholar
  3. 3.
    Barraud, S., Berthomé, M., Coquand, R., et al.: Scaling of trigate junctionless nanowire MOSFET with gate length down to 13 nm. IEEE Electron Device Lett. 33(9), 1225–1227 (2012)CrossRefGoogle Scholar
  4. 4.
    Lou, H., Zhang, L., Zhu, Y., et al.: A junctionless nanowire transistor with a dual-material gate. IEEE Trans. Electron Devices 59(7), 1829–1836 (2012)CrossRefzbMATHGoogle Scholar
  5. 5.
    Liu, X., Wu, M., Jin, X., Chuai, R., Lee, J.-H.: Simulation study on deep nanoscale short channel junctionless SOI FinFETs with triple-gate or double-gate structures. J. Comput. Electron. 13(2), 509–514 (2014)CrossRefGoogle Scholar
  6. 6.
    Wu, M., Jin, X., Kwon, H.-I., et al.: The optimal design of junctionless transistors with double-gate structure for reducing the effect of band-to-band tunneling. J. Semicond. Technol. Sci. 13(2), 245–251 (2013)Google Scholar
  7. 7.
    Liu, X., Wu, M., Jin, X., Chuai, R., Lee, J.-H., Lee, J.-H.: The optimal design of 15 nm gate-length junctionless SOI FinFETs for reducing leakage current. Semicond. Sci. Technol. 28, 105013 (2013)CrossRefGoogle Scholar
  8. 8.
    Lee, C.W., Afzalian, A., Akhavan, N.D., Yan, R., Ferain, I., Colinge, J.P.: Junction-less multigate field-effect transistor. Appl. Phys. Lett. 94, 053511 (2009)CrossRefGoogle Scholar
  9. 9.
    Su, C.-J., Tsai, T.-I., Liou, Y.-L., Lin, Z.-M., et al.: Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels. IEEE Electron Device Lett. 32(4), 521–523 (2011)CrossRefGoogle Scholar
  10. 10.
    Jin, X., Liu, X., Wu, M., Chuai, R., Lee, J.-H., Lee, J.-H.: Modelling of the nanoscale channel length effect on the subthreshold characteristics of junctionless field-effect transistors with a symmetric double-gate structure. J. Phys. D 45, 375102 (2012)CrossRefGoogle Scholar
  11. 11.
    Jin, X., Liu, X., Chuai, R., Lee, J.H., Lee, J.H.: A compact model of subthreshold characteristics for short channel double-gate junctionless field effect transistors. Eur. Phys. J. Appl. Phys. 65, 30101 (2014)CrossRefGoogle Scholar
  12. 12.
    Jin, X., Liu, X., Lee, J.-H., Lee, J.H.: Modeling of subthreshold characteristics of short channel junctionless cylindrical surrounding-gate nanowire metal–oxide–silicon field effect transistors. Phys. Scr. 89, 015804 (2014)CrossRefGoogle Scholar
  13. 13.
    Park, K.-H., Han, K.-R., Kim, Y.M., et al.: Simulation study of high-performance modified saddle MOSFET for sub-50-nm DRAM cell transistors. IEEE Electron Device Lett. 27(2), 759–761 (2006)CrossRefGoogle Scholar
  14. 14.
    SILVACO International: ATLAS User’s Manual (2012)Google Scholar
  15. 15.
    Shoji, M., Horiguchi, S.: Electronic structures and phonon-limited electron mobility of double-gate silicon-on-insulator Si inversion layers. J. Appl. Phys. 85, 2722–2731 (1999)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Xiaoshi Jin
    • 1
    Email author
  • Meile Wu
    • 1
  • Xi Liu
    • 1
  • Rongyan Chuai
    • 1
  • Hyuck-In Kwon
    • 2
  • Jung-Hee Lee
    • 3
  • Jong-Ho Lee
    • 4
  1. 1.School of Information Science and EngineeringShenyang University of TechnologyShenyangChina
  2. 2.School of Electrical and Electronics EngineeringChung-Ang UniversitySeoulKorea
  3. 3.School of EECSKyungpook National UniversityDaeguKorea
  4. 4.School of EECS Engineering and ISRC (Inter-University Semiconductor Research Center)Seoul National UniversitySeoulKorea

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