A novel high performance junctionless FETs with saddle-gate
- 485 Downloads
In this paper, a novel junctionless field effect transistors (JL FETs) with a saddle-gate structure has been proposed, and the I–V characteristics has been extensively studied by TCAD device simulation. The performance comparison between saddle-gate JL FETs and conventional triple-gate JL FETs has also been performed. The influence of gate dielectric on device property has also been investigated. A scheme of design optimization of saddle-gate JL FETs has also been proposed.
KeywordsSaddle-gate Junctionless Field effect transistors Design optimization
This work is supported by the Fund of Liaoning Province Education Department No. L2012028, No. L2013045, the fund of the ministry of education of China, and the National Natural Science Foundation of China No. 61372019.
- 6.Wu, M., Jin, X., Kwon, H.-I., et al.: The optimal design of junctionless transistors with double-gate structure for reducing the effect of band-to-band tunneling. J. Semicond. Technol. Sci. 13(2), 245–251 (2013)Google Scholar
- 14.SILVACO International: ATLAS User’s Manual (2012)Google Scholar