Journal of Computational Electronics

, Volume 14, Issue 3, pp 661–668 | Cite as

A novel high performance junctionless FETs with saddle-gate

  • Xiaoshi JinEmail author
  • Meile Wu
  • Xi Liu
  • Rongyan Chuai
  • Hyuck-In Kwon
  • Jung-Hee Lee
  • Jong-Ho Lee


In this paper, a novel junctionless field effect transistors (JL FETs) with a saddle-gate structure has been proposed, and the I–V characteristics has been extensively studied by TCAD device simulation. The performance comparison between saddle-gate JL FETs and conventional triple-gate JL FETs has also been performed. The influence of gate dielectric on device property has also been investigated. A scheme of design optimization of saddle-gate JL FETs has also been proposed.


Saddle-gate Junctionless Field effect transistors Design optimization 



This work is supported by the Fund of Liaoning Province Education Department No. L2012028, No. L2013045, the fund of the ministry of education of China, and the National Natural Science Foundation of China No. 61372019.


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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Xiaoshi Jin
    • 1
    Email author
  • Meile Wu
    • 1
  • Xi Liu
    • 1
  • Rongyan Chuai
    • 1
  • Hyuck-In Kwon
    • 2
  • Jung-Hee Lee
    • 3
  • Jong-Ho Lee
    • 4
  1. 1.School of Information Science and EngineeringShenyang University of TechnologyShenyangChina
  2. 2.School of Electrical and Electronics EngineeringChung-Ang UniversitySeoulKorea
  3. 3.School of EECSKyungpook National UniversityDaeguKorea
  4. 4.School of EECS Engineering and ISRC (Inter-University Semiconductor Research Center)Seoul National UniversitySeoulKorea

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