1/f Noise: threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps
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Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation—two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO2 interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO2 interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.
KeywordsRandom dopant fluctuations Random telegraph noise fluctuations Monte Carlo device simulations
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- 5.Kurata, H., Otsuga, K., Kotabe, A., Kajiyama, S., Osabe, T., Sasago, Y., Narumi, S., Tokami, K., Kamohara, S., Tsuchiya, O.: The impact of random telegraph signals on the scaling of multilevel flash memories. In: Symposium on VLSI Circuits, pp. 125–126 (2006) Google Scholar
- 6.Tega, N., Miki, H., Osabe, T., Kotabe, A., Otsuga, K., Kurata, H., Kamohara, S., Tokami, K., Ikeda, Y., Yamada, R.: Anomalously large threshold voltage fluctuation by complex random telegraph signal in floating gate flash memory. In: Technical Digest of International Electron Devices Meeting, pp. 491–494 (2006) Google Scholar
- 7.Tega, N., Miki, H., Yamaoka, M., Kume, H., Mine, T., Ishida, T., Mori, Y., Yamada, R., Torii, K.: Impact of threshold voltage fluctuation due to random telegraph noise on scaled-down SRAM. In: IEEE 46th Annual International Reliability Physics Symposium, pp. 541–546 (2008) Google Scholar
- 8.Agnostinelli, M., Hicks, J., Xu, J., Woolery, B., Mistry, K., Zhang, K., Jacobs, S., Jopling, J., Yang, W., Lee, B., Raz, T., Mehalel, M., Kolar, P., Wang, Y., Sandford, J., Pivin, D., Peterson, C., Di Battista, M., Pae, S., Jones, M., Johnson, S., Subramanian, G.: Erratic fluctuations of SRAM cache V min at the 90 nm process technology node, Tech. Dig. Int. Electron Devices Meet., 655–658 (2005) Google Scholar
- 12.Wong, H.S., Taur, Y.: Three-dimensional “atomistic” simulation of discrete random dopant distribution effects in Sub-0.1 μm MOSFET’s. In: Proceedings of IEDM, pp. 29.2.1–29.2.4 (1993) Google Scholar