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Journal of Computational Electronics

, Volume 7, Issue 3, pp 124–127 | Cite as

Capacitance variability of short range interconnects

  • Timothy D. DrysdaleEmail author
  • Andrew R. Brown
  • Gareth Roy
  • Scott Roy
  • Asen Asenov
Article

Abstract

End of the roadmap integrated circuit interconnects suffer from capacitance variability due to line edge roughness (LER), significantly impacting overall circuit performance. We forecast the capacitance variability of short range interconnects with realistic line edge roughness at the upcoming 45, 32, and 22 nm technology nodes using a fast TCAD capacitance tool. Capacitance variability is layout sensitive and worsens with reduction in feature size, and together with the increasing device variability requires inclusion in statistical models of standard cells from the 45 nm node onwards. If LER does not improve then, for example, by the 22 nm node, short parallel lines on metal 1 are predicted to have 12% variability and, depending on layout, SRAM bit line capacitance 7% variability.

Keywords

Interconnect Variability Standard cell Capacitance 6T SRAM 

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References

  1. 1.
    Samsudin, K., Cheng, B., Brown, A.R., Roy, S., Asenov, A.: Integrating intrinsic parameter fluctuation description into BSIMSOI to forecast sub-15nm UTB SOI based 6T SRAM operation. Solid State Electron. 50, 86 (2006) CrossRefGoogle Scholar
  2. 2.
    Meindl, J.D.: Interconnect opportunities for gigascale integration. IEEE Micro 23(3), 28–35 (2003) CrossRefGoogle Scholar
  3. 3.
    Yamaguchi, T., Namatsu, H., Nagase, M., Yamazaki, K., Kurihara, K.: Nanometer-scale linewidth fluctuations caused by polymer aggregates in resist films. Appl. Phys. Lett. 71(16), 2388–2390 (1997) CrossRefGoogle Scholar
  4. 4.
    Namatsu, H., Nagase, M., Yamaguchi, T., Yamazaki, K., Kurihara, K.: Influence of edge roughness in resist patterns on etched patterns. J. Vac. Sci. Technol. B 16, 3315–3321 (1998) CrossRefGoogle Scholar
  5. 5.
    Steinhögl, W., et al.: Microelectron. Eng. 76, 126–130 (2004) CrossRefGoogle Scholar
  6. 6.
    Weste, N.H.E., Harris, D.: CMOS VLSI Design, 3rd edn. Addison Wesley, Boston (2005) Google Scholar
  7. 7.
    Asenov, A., Kaya, S., Brown, A.R.: Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness. IEEE Tran. Electron. Dev. 50(5), 1254–1260 (2003) CrossRefGoogle Scholar
  8. 8.
    Chern, J.-H., Huang, J., Arledge, L., Li, P.-C., Yang, P.: Multilevel metal capacitance models for CAD design synthesis systems. IEEE Electron. Dev. Lett. 13, 32 (1992) CrossRefGoogle Scholar
  9. 9.
    Tosik, G., Lisik, Z., Langer, M., Wozny, J.: Simulation of parasitic interconnect capacitance for present and future ICs. Proc. Int. Conf. Comp. Sci. 3514, 607–614 (2005) Google Scholar
  10. 10.
    Cumming, D.R.S.: Improved VLSI interconnect. Int. J. Electron. 86(8), 957–965 (1999) CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media LLC 2007

Authors and Affiliations

  • Timothy D. Drysdale
    • 1
    Email author
  • Andrew R. Brown
    • 2
  • Gareth Roy
    • 2
  • Scott Roy
    • 2
  • Asen Asenov
    • 2
  1. 1.Electronics Design CentreUniversity of GlasgowGlasgowUK
  2. 2.Device Modelling GroupUniversity of GlasgowGlasgowUK

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