Journal of Computational Electronics

, Volume 4, Issue 1–2, pp 119–123 | Cite as

Search for Optimum and Scalable COSMOS

  • Savas KayaEmail author
  • Ahmad Al-Ahmadi


We introduce a novel CMOS device architecture capable of building complementary logic operation using only a single gate stack. The new architecture, named complementary orthogonal stacked MOS (COSMOS), places the n and p-MOSFETs perpendicular to one another under a single gate, integrating them vertically as well as laterally. The COSMOS architecture would not only mean significant savings in active device area of a conventional static CMOS pair, but also significant reductions in RC device parasitics. We demonstrate how the device may be built, operated and optimized for symmetric operation, as well as verifying logic NOT operation via 3D device simulations. COSMOS architecture appears to have peculiar scaling trends such as increasing threshold at reduced gate dimensions. The increase in drive voltages lead to faster operation at the expense of higher static leakage and loss of noise margins.


CMOS integrated circuits silicon on insulator technology silicon germanium alloys ultra-large-scale integration leakage currents 


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Copyright information

© Springer Science + Business Media, Inc. 2005

Authors and Affiliations

  1. 1.School of Electrical Engineering and Computer Science, Russ College of Engineering and TechnologyOhio UniversityAthensUSA

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