A Computational Model of NBTI and Hot Carrier Injection Time-Exponents for MOSFET Reliability
- 348 Downloads
Theories of interface trap generation in Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) mechanisms are unified under the geometric interpretation and computational modeling of Reaction-Diffusion (R-D) theoryframework. Analytical derivations that predict the degradation are shown, simulation methodology is explained and numerical solutions are obtained. Time-exponents and degradation behavior under dynamic bias in agreement with experimental observations are discussed. Implications regarding ultra-scaled surround-gate device structures are presented.
KeywordsMOSFET reliability NBTI HCI reaction diffusion surround-gate
Unable to display preview. Download preview PDF.
- 1.V. Huard et al., “Hole trapping effect on methodology for DC and AC negative bias temperature instability measurments in PMOS transistors,” IEEE IRPS, 2004, p. 40.Google Scholar
- 3.K.O. Jeppson et al., “Negative bias of MOS devices at high electric fields and degradation of MNOS devices,” JAP, 48, 1977 (2004).Google Scholar
- 4.M.A. Alam, “A critical examination of the mechanics of dynamic NBTI for PMOSFETs,” IEDM Technical Digest, 345, (Dec. 2003).Google Scholar
- 5.H. Kufluoglu et al., “A geometrical unification of the theories of NBTI and HCI time-exponents and its implications for ultra-scaled planar and surround-gate MOSFETS,” IEDM Technical Digest. IEEE International 13–15 Dec. 2004, 113–116.Google Scholar
- 6.T. Wang et al., “A comprehensive study of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs,” TED, 46(9), 1877 (1999).Google Scholar
- 8.D. Ang et al., “A new insight into the degradation behavior of the LDD N-MOSFET during dynamic hot-carrier stress ing,” EDL 22(11), 553 (2001) & “A reassessment of AC hot-carrier degradation in deep-submicrometer LDD N-MOSFET,” EDL 24(9), 598 (2003).Google Scholar
- 10.S. Maeda et al., “Negative bias temperature instability in triple gate transistors,” IRPS Proceedings (2004), p. 8.Google Scholar