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International Journal of Parallel Programming

, Volume 45, Issue 6, pp 1515–1535 | Cite as

GPU Parallelization of HEVC In-Loop Filters

  • Biao Wang
  • Diego F. de Souza
  • Mauricio Alvarez-Mesa
  • Chi Ching Chi
  • Ben Juurlink
  • Aleksandar Ilic
  • Nuno Roma
  • Leonel Sousa
Article

Abstract

In the High Efficiency Video Coding (HEVC) standard, multiple decoding modules have been designed to take advantage of parallel processing. In particular, the HEVC in-loop filters (i.e., the deblocking filter and sample adaptive offset) were conceived to be exploited by parallel architectures. However, the type of the offered parallelism mostly suits the capabilities of multi-core CPUs, thus making a real challenge to efficiently exploit massively parallel architectures such as Graphic Processing Units (GPUs), mainly due to the existing data dependencies between the HEVC decoding procedures. In accordance, this paper presents a novel strategy to increase the amount of parallelism and the resulting performance of the HEVC in-loop filters on GPU devices. For this purpose, the proposed algorithm performs the HEVC filtering at frame-level and employs intrinsic GPU vector instructions. When compared to the state-of-the-art HEVC in-loop filter implementations, the proposed approach also reduces the amount of required memory transfers, thus further boosting the performance. Experimental results show that the proposed GPU in-loop filters deliver a significant improvement in decoding performance. For example, average frame rates of 76 frames per second (FPS) and 125 FPS for Ultra HD 4K are achieved on an embedded NVIDIA GPU for All Intra and Random Access configurations, respectively.

Keywords

High Efficiency Video Coding (HEVC) Graphics Processor Unit (GPU) In-loop filters Parallelization Decoder 

Notes

Acknowledgements

This work was supported by national funds through FCT, under projects PTDC/EEI-ELC/3152/2012 and UID/CEC/50021/2013. Diego F. de Souza also acknowledges FCT for the Ph.D. scholarship SFRH/BD/76285/2011.

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Copyright information

© Springer Science+Business Media New York 2017

Authors and Affiliations

  • Biao Wang
    • 1
  • Diego F. de Souza
    • 2
  • Mauricio Alvarez-Mesa
    • 1
  • Chi Ching Chi
    • 1
  • Ben Juurlink
    • 1
  • Aleksandar Ilic
    • 2
  • Nuno Roma
    • 2
  • Leonel Sousa
    • 2
  1. 1.AES, Technische Universität BerlinBerlinGermany
  2. 2.INESC-ID, IST, Universidade de LisboaLisbonPortugal

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