International Journal of Parallel Programming

, Volume 45, Issue 5, pp 1026–1045 | Cite as

Energy-Aware Modeling of Scaled Heterogeneous Systems

  • Ami Marowka


Many-core processors are accelerating the performance of contemporary high-performance systems. Managing power consumption within these systems demands low-power architectures to increase power savings. One of the promising solutions offered today by microprocessor architects is asymmetric microprocessors that integrate different core architectures on a single die. This paper presents analytical models based on scaled power metrics to analyze the impact of various architectural design choices on scaled performance and power savings. The power consumption implications of different processing schemes and various chip configurations were also analyzed. Analysis shows that by choosing the optimal chip configuration, energy efficiency and energy savings can be increased considerably.


Energy efficiency Gustafson–Barsis’s law Hybrid architecture Performance per Watt Modeling techniques 


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Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  1. 1.Parallel Research LabTel AvivIsrael

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