Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis

  • Alexander Czutro
  • Ilia PolianEmail author
  • Matthew Lewis
  • Piet Engelke
  • Sudhakar M. Reddy
  • Bernd Becker


Efficient utilization of the inherent parallelism of multi-core architectures is a grand challenge in the field of electronic design automation (EDA). One EDA algorithm associated with a high computational cost is automatic test pattern generation (ATPG). We present the ATPG tool TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models. We demonstrate how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches.


Thread-parallel SAT SAT-based automatic test pattern generation 


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Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  • Alexander Czutro
    • 1
  • Ilia Polian
    • 1
    Email author
  • Matthew Lewis
    • 1
  • Piet Engelke
    • 1
  • Sudhakar M. Reddy
    • 2
  • Bernd Becker
    • 1
  1. 1.Computer Architecture Group, Institute for Computer ScienceAlbert-Ludwigs-UniversityFreiburg i. Br.Germany
  2. 2.ECE DepartmentUniversity of IowaIowa CityUSA

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