International Journal of Parallel Programming

, Volume 36, Issue 5, pp 457–477 | Cite as

A Flexible Framework for Communication Evaluation in SoC Design

  • Praveen Kalla
  • X. Sharon Hu
  • Jörg Henkel


Multi-core System-on-Chips (SoCs) with on-chip networks are becoming a reality after almost a decade of research. One challenge in developing such SoCs is the need of efficient and accurate simulators for design space exploration. This paper addresses this need by presenting SoCExplore, a framework for fast communication-centric design space exploration of complex SoCs with network-based interconnects. Efficiency is achieved through abstraction of computation as a high-level trace, while accuracy is maintained through cycle-accurate interconnect simulation. The flexibility offered allows for fast partition/mapping and interconnect design space exploration. In a case study, a speed-up of 94% over architectural simulation is obtained for the MPEG application. A critical evaluation of the capabilities of our (or any trace based) framework is also provided.


Multiprocessor simulator Interconnect simulator Network on chip Trace based simulation 


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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  1. 1.BroadcomMatawanUSA
  2. 2.Department of Computer Science and EngineeringUniversity of Notre DameNotre DameUSA
  3. 3.Department of Computer ScienceUniversity of KarlsruheKarlsruheGermany

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