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International Journal of Parallel Programming

, Volume 36, Issue 5, pp 457–477 | Cite as

A Flexible Framework for Communication Evaluation in SoC Design

  • Praveen Kalla
  • X. Sharon Hu
  • Jörg Henkel
Article

Abstract

Multi-core System-on-Chips (SoCs) with on-chip networks are becoming a reality after almost a decade of research. One challenge in developing such SoCs is the need of efficient and accurate simulators for design space exploration. This paper addresses this need by presenting SoCExplore, a framework for fast communication-centric design space exploration of complex SoCs with network-based interconnects. Efficiency is achieved through abstraction of computation as a high-level trace, while accuracy is maintained through cycle-accurate interconnect simulation. The flexibility offered allows for fast partition/mapping and interconnect design space exploration. In a case study, a speed-up of 94% over architectural simulation is obtained for the MPEG application. A critical evaluation of the capabilities of our (or any trace based) framework is also provided.

Keywords

Multiprocessor simulator Interconnect simulator Network on chip Trace based simulation 

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References

  1. 1.
  2. 2.
    Intel 80 core prototype: http://www.intel.com/pressroom/archive/ releases/20060926corp.htm
  3. 3.
    Borkar, S.: Electronics beyond nano-scale CMOS. DAC (2006)Google Scholar
  4. 4.
    Benini, L., De Micheli, G.: Networks on chip: a new SOC paradigm. IEEE Comput. 70–78 (2002)Google Scholar
  5. 5.
    Dally, W.J., Towles, B.: Route packets not wires: on-chip interconnection networks. DAC (2001)Google Scholar
  6. 6.
    Karim, F., Nyugen, A., Dey, S.: An interconnect architecture for networking systems on chips. IEEE Micro (2002)Google Scholar
  7. 7.
    Wang, H.S., Zhu, X., Peh, L.S., Malik, S.: Orion: a power-performance simulator for interconnection networks. MICRO 35, Nov. 2002Google Scholar
  8. 8.
    Kogel, T., et al.: A modular simulation framework for architectural exploration of on-chip interconnection networks. CODES+ISSS, pp. 7–12 (2003)Google Scholar
  9. 9.
    Xi, J., Zhong, P.: A system-level network-on-chip simulation framework integrated with low-Level analytical models. ICCD (2006)Google Scholar
  10. 10.
    Brinkmann, A., et al.: On-chip interconnects for next generation system-on-chips. In: 15th Annual IEEE International ASIC/SOC Conference (2002)Google Scholar
  11. 11.
    Pestana, S., Rijkema, E., et al.: Cost-performance trade-offs in networks on chip: a simulation-based approach. DATE (2004)Google Scholar
  12. 12.
    Lu, Z., Thid, R., Millberg, M., Nilsson, E., Jantsch, A.: NNSE: nostrum network-on-chip simulation environment. In: Swedish System on Chip Conf. (2005)Google Scholar
  13. 13.
    Scherrer, A., Fraboulet, A., Risset, T.: Automatic phase detection for stochastic on-chip traffic generation. CODES (2006)Google Scholar
  14. 14.
    Tedesco, L., Mello, A., Giacomet, L., Calazans, N., Moraes, F.: Application driven traffic modeling for NoCs. SBCCI (2006)Google Scholar
  15. 15.
    Lahiri, K., Raghunathan, A., Dey, S.: System-level performance analysis for on-chip communication architectures. TCAD (2001)Google Scholar
  16. 16.
    Dumitrascu, F., Bacivarov, I., Pieralisi, L., Bonaciu, M., Jerraya, A.A.: Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application. DATE (2006)Google Scholar
  17. 17.
    Kim, S., Im, C., Ha, S.: Schedule-aware performance estimation pf communication architecture for efficient design space exploration. CODES+ISSS (2003)Google Scholar
  18. 18.
    Genko, N., Micheli, G.D., et al.: A complete network-On-chip emulation framework. DATE (2005)Google Scholar
  19. 19.
    Zivkovic, V.D., et al.: Fast and accurate multiprocessor architecture exploration with symbolic programs. DATE (2003)Google Scholar
  20. 20.
    Palermo, G., Silvano, C.: PIRATE: a framework for power/performance exploration of network- on-chip architectures. PATMOS (2004)Google Scholar
  21. 21.
    Ching, D., Schaumont, P., Verbauwhede, I.: Integrated modeling and generation of a reconfigurable network-on-chip. In: IPDPS Workshop, p. 139 (2004)Google Scholar
  22. 22.
  23. 23.

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  1. 1.BroadcomMatawanUSA
  2. 2.Department of Computer Science and EngineeringUniversity of Notre DameNotre DameUSA
  3. 3.Department of Computer ScienceUniversity of KarlsruheKarlsruheGermany

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