International Journal of Parallel Programming

, Volume 36, Issue 3, pp 347–360

Performance Advantage of Reconfigurable Cache Design on Multicore Processor Systems

  • Jie Tao
  • Marcel Kunze
  • Fabian Nowak
  • Rainer Buchty
  • Wolfgang Karl
Article

DOI: 10.1007/s10766-008-0075-4

Cite this article as:
Tao, J., Kunze, M., Nowak, F. et al. Int J Parallel Prog (2008) 36: 347. doi:10.1007/s10766-008-0075-4

Abstract

With the trends of microprocessor design towards multicore, cache performance becomes more important because an off-chip access would be increasingly expensive due to the competition across the processor cores. A question arises: How to design the cache architecture to prevent a performance bottleneck caused by data accesses? This work studies a reconfigurable cache architecture that can be dynamically configured for meeting the individual demand of running applications. Using a self-developed cache simulator, we first examined how different cache organization and configuration influence the parallel execution of OpenMP applications. The experimental results show that applications benefit from a flexible cache with reconfigurability. This motivated us to go a step further and develop a hardware prototype of this novel architecture.

Keywords

Cache performance Multicore processor Simulation Reconfigurable architecture 

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Jie Tao
    • 1
    • 2
  • Marcel Kunze
    • 2
  • Fabian Nowak
    • 3
  • Rainer Buchty
    • 3
  • Wolfgang Karl
    • 3
  1. 1.Department of Computer Science and TechnologyJilin UniversityChangchunPeople’s Republic of China
  2. 2.Steinbuch Centre for Computing, Forschungszentrum KarlsruheKarlsruhe Institute of TechnologyKarlsruheGermany
  3. 3.Institut für Technische InformatikUniversität Karlsruhe, Karlsruhe Institute of  TechnologyKarlsruheGermany

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