International Journal of Parallel Programming

, Volume 35, Issue 6, pp 529–572 | Cite as

Parallel Algorithms Development for Programmable Devices with Application from Cryptography

  • Issam W. DamajEmail author

Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), have been witnessing a considerable increase in density. State-of-the-art FPGAs are complex hybrid devices that contain up to several millions of gates. Recently, research effort has been going into higher-level parallelization and hardware synthesis methodologies that can exploit such a programmable technology. In this paper, we explore the effectiveness of one such formal methodology in the design of parallel versions of the Serpent cryptographic algorithm. The suggested methodology adopts a functional programming notation for specifying algorithms and for reasoning about them. The specifications are realized through the use of a combination of function decomposition strategies, data refinement techniques, and off-the-shelf refinements based upon higher-order functions. The refinements are inspired by the operators of Communicating Sequential Processes and map easily to programs in Handel-C (a hardware description language). In the presented research, we obtain several parallel Serpent implementations with different performance characteristics. The developed designs are tested under Celoxica’s RC-1000 reconfigurable computer with its two million gates Virtex-E FPGA. Performance analysis and evaluation of these implementations are included.


Parallel algorithms methodologies data encryption formal models gate array 


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© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  1. 1.Dhofar UniversitySalalahOman

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