International Journal of Parallel Programming

, Volume 35, Issue 2, pp 125–156

Fault-aware Communication Mapping for NoCs with Guaranteed Latency

Special Issue

As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival probability and response time. We address the problem of transient link failures by means of temporally and spatially redundant transmission of messages, such that designer-imposed message arrival probabilities are guaranteed. Response time minimisation is achieved by a heuristic that statically assigns multiple copies of each message to network links, intelligently combining temporal and spatial redundancy. Concerns regarding energy consumption are addressed in two ways. First, we reduce the total amount of transmitted messages, and, second, we minimise the application response time such that the resulted time slack can be exploited for energy savings through voltage reduction. The advantages of the proposed approach are guaranteed message arrival probability and guaranteed worst case application response time.

Keywords

Networks-on-chip communication synthesis transient link failures 

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References

  1. 1.
    Diefenderhoff K. (2000). Extreme Lithography. Microprocessor Rep. 6(19): 1–10Google Scholar
  2. 2.
    K. Shepard and V. Narayanan, Noise in Deep Submicron Digital Design, in Proc. of the ICCAD, pp. 524–531 (1996).Google Scholar
  3. 3.
    K. Aingaran, F. Klass, C. M. Kim, C. Amir, J. Mitra, E. You, J. Mohd, and S. K. Dong, Coupling Noise Analysis for VLSI and ULSI Circuits, in Proc. of IEEE ISQED, pp. 485–489 (2000).Google Scholar
  4. 4.
    Benini L., De Micheli G. (2002). Networks on Chips: A New SoC Paradigm. IEEE Comput. 35(1):70–78Google Scholar
  5. 5.
    Goossens K., Dielissen J., Radulescu A. (2005). AEthereal Network on Chip: Concepts, Architectures and Implementations. IEEE. Des. Test. Comput. 22(5):414–421CrossRefGoogle Scholar
  6. 6.
    S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. Öberg, K. Tiensyrjä, and A. Hemani, A Network on Chip Architecture and Design Methodology, in Proc. of the IEEE Computer Society Annual Symposium on VLSI, pp. 105–112 (2002).Google Scholar
  7. 7.
    W. Dally, Interconnect-limited VLSI Architecture, in Proc. of the IEEE Conference on Interconnect Technologies, pp. 15–17 (1999).Google Scholar
  8. 8.
    D. Liu et al., Power Consumption Estimation in CMOS VLSI chips, IEEE J. Solid-State Circ., (29):663–670 (1994).Google Scholar
  9. 9.
    Hu J., Mărculescu R. (2005). Energy and Performance-aware Mapping for Regular NoC Architectures. IEEE Trans. CAD Integr. Circ. Syst. 24(4):551–562CrossRefGoogle Scholar
  10. 10.
    S. Murali and G. De Micheli, Bandwidth-constrained Mapping of Cores onto NoC architectures, in Proc. of the Conference on Design Automation and Test in Europe, pp. 896–901 (2004).Google Scholar
  11. 11.
    Bolotin E., Cidon I., Ginosar R., Kolodny A. (2004) QNoC: QoS architecture and Design Process for Networks-on-chip. J. Syst. Arch. 50:105–128CrossRefGoogle Scholar
  12. 12.
    Kermani P., Kleinrock L. (1979). Virtual Cut-Through: A New Computer Communication Switching Technique. Comput. Netw. 3(4):267–286MATHCrossRefMathSciNetGoogle Scholar
  13. 13.
    T. Dumitraş and R. Mărculescu, On-chip Stochastic Communication, in Proc. of DATE, pp. 790–795 (2003).Google Scholar
  14. 14.
    S. Manolache, Fault-tolerant Communication on Network-on-chip, Technical report, Linköping University (2004).Google Scholar
  15. 15.
    M. Pirretti, G. M. Link, R. R. Brooks, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, Fault Tolerant Algorithms for Network-on-chip Interconnect, in Proc. of the ISVLSI, pp. 46–51 (2004).Google Scholar
  16. 16.
    D. Bertozzi, L. Benini, and G. De Micheli, Low Power Error Resilient Encoding for On-chip Data Buses, in Proc. of DATE, pp. 102–109 (2002).Google Scholar
  17. 17.
    T. T. Ye, L. Benini, and G. De Micheli, Analysis of Power Consumption on Switch Fabrics in Network routers, in Proc. of DAC, pp. 524–529 (2002).Google Scholar
  18. 18.
    J. C. Palencia Gutiérrez and M. González Harbour, Schedulability Analysis for Tasks with Static and Dynamic Offsets, in Proc. of the 19th IEEE Real Time Systems Symposium, pp. 26–37 (December 1998).Google Scholar
  19. 19.
    Glover F. (1989). Tabu Search—Part I. ORSA J. Comput. 1(3):190–206MATHGoogle Scholar
  20. 20.
    Alippi C., Galbusera A., Stellini M. (2003). An Application-level Synthesis Methodology for Multidimensional Embedded Processing Systems. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 22(11):1457–1470CrossRefGoogle Scholar
  21. 21.
    Traferro S., Capparelli F., Piazza F., Uncini A. (1999). Efficient Allocation of Power of Two Terms in FIR Digital Filter Design using Tabu Search. IEEE Trans. Comput. Aided Des. Integr. Circ. and Syst. 3:411–414Google Scholar
  22. 22.
    T. Wild, J. Foag, N. Pazos, and W. Brunnbauer, Mapping and Scheduling for Architecture Exploration of Networking SoCs, in Proc. of the 16th International Conference on VLSI Design, pp. 376–381 (2003).Google Scholar
  23. 23.
    R. S. Cardoso, M. E. Kreutz, L. Carro, and A. A. Susin, Design Space Exploration on Heterogeneous Network-on-chip, in Proc. of the IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 428–431 (2005).Google Scholar
  24. 24.
    Hajji O., Brisset S., Brochet P. (2002). Comparing Stochastic Optimization Methods used in Electrical Engineering. IEEE Trans. Syst. Man Cybern 7(6–9):6CrossRefGoogle Scholar
  25. 25.
    Pierre S., Houeto F. (2002). Assigning Cells to Switches in Cellular Mobile Networks Using Taboo Search. IEEE Trans. Syst. Man Cybern 32(3):351–356CrossRefGoogle Scholar
  26. 26.
    B. Krishnamachari and S. B. Wicker, Optimization of Fixed Network Design in Cellular Systems using Local Search Algorithms, in Proc. of the 52nd Vehicular Technology Conference, Vol. 4, pp. 1632–1638 (2000).Google Scholar
  27. 27.
    Eles P., Peng Z., Kuchcinsky K., Doboli A. (1997). System-level Hardware/software Partitioning Based on Simulated Annealing and Tabu Search. J. Des. Autom. Embed. Sys. 2:5–32CrossRefGoogle Scholar
  28. 28.
    A. Andrei, M. Schmitz, P. Eles, Z. Peng, and B. Al-Hashimi, Simultaneous Communication and Processor Voltage Scaling for Dynamic and Leakage Energy Reduction in Time-constrained Systems, in Proc. of ICCAD, pp. 362–369 (2004).Google Scholar
  29. 29.
    International Telecommunication Union (ITU). H.263Video coding for low bit rate communication, 2005. http://www.itu.int/publications/itu-t/.Google Scholar
  30. 30.
    International Organization for Standardization (ISO). ISO/IEC 11172-3:1993 – Coding of moving pictures and associated audio for digital storage media at up to about 1,5 Mbit/s – Part 3: Audio, 1993. http://www.iso.org/.Google Scholar
  31. 31.
    J. Hu and R. Mărculescu, Energy-aware Communication and Task Scheduling for Network-on-chip Architectures Under Real-time Constraints, in Proc. of the Design Automation and Test in Europe Conference, p. 10234 (2004).Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2006

Authors and Affiliations

  1. 1.Department of Computer and Information ScienceLinköping UniversityLinköpingSweden

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