International Journal of Parallel Programming

, Volume 35, Issue 2, pp 125–156

Fault-aware Communication Mapping for NoCs with Guaranteed Latency

Special Issue

DOI: 10.1007/s10766-006-0029-7

Cite this article as:
Manolache, S., Eles, P. & Peng, Z. Int J Parallel Prog (2007) 35: 125. doi:10.1007/s10766-006-0029-7

As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival probability and response time. We address the problem of transient link failures by means of temporally and spatially redundant transmission of messages, such that designer-imposed message arrival probabilities are guaranteed. Response time minimisation is achieved by a heuristic that statically assigns multiple copies of each message to network links, intelligently combining temporal and spatial redundancy. Concerns regarding energy consumption are addressed in two ways. First, we reduce the total amount of transmitted messages, and, second, we minimise the application response time such that the resulted time slack can be exploited for energy savings through voltage reduction. The advantages of the proposed approach are guaranteed message arrival probability and guaranteed worst case application response time.


Networks-on-chip communication synthesis transient link failures 

Copyright information

© Springer Science+Business Media, LLC 2006

Authors and Affiliations

  1. 1.Department of Computer and Information ScienceLinköping UniversityLinköpingSweden

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