Genetic Programming and Evolvable Machines

, Volume 12, Issue 3, pp 305–327 | Cite as

Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware

  • Zdenek Vasicek
  • Lukas SekaninaEmail author


We propose to utilize a formal verification algorithm to reduce the fitness evaluation time for evolutionary post-synthesis optimization in evolvable hardware. The proposed method assumes that a fully functional digital circuit is available. A post-synthesis optimization is then conducted using Cartesian Genetic Programming (CGP) which utilizes a satisfiability problem solver to decide whether a candidate solution is functionally correct or not. It is demonstrated that the method can optimize digital circuits of tens of inputs and thousands of gates. Furthermore, the number of gates was reduced for the LGSynth93 benchmark circuits by 37.8% on average with respect to results of the conventional SIS tool.


Cartesian genetic programming Circuit optimization SAT solver Evolvable hardware 



This work was partially supported by the Czech Science Foundation under projects Natural Computing on Unconventional Platforms P103/10/1517 and Mathematical and Engineering Approaches to Developing Reliable and Secure Concurrent and Distributed Computer Systems GD102/09/H042 and by the research programme Security-Oriented Research in Information Technology MSM 0021630528.


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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.Faculty of Information TechnologyBrno University of TechnologyBrnoCzech Republic

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