Advertisement

Genetic Programming and Evolvable Machines

, Volume 10, Issue 3, pp 231–262 | Cite as

A three-step decomposition method for the evolutionary design of sequential logic circuits

  • Houjun Liang
  • Wenjian LuoEmail author
  • Xufa Wang
Original Paper

Abstract

Evolvable hardware (EHW) refers to an automatic circuit design approach, which employs evolutionary algorithms (EAs) to generate the configurations of the programmable devices. The scalability is one of the main obstacles preventing EHW from being applied to real-world applications. Several techniques have been proposed to overcome the scalability problem. One of them is to decompose the whole circuit into several small evolvable sub-circuits. However, current techniques for scalability are mainly used to evolve combinational logic circuits. In this paper, in order to decompose a sequential logic circuit, the state decomposition, output decomposition and input decomposition are united as a three-step decomposition method (3SD). A novel extrinsic EHW system, namely 3SD–ES, which combines the 3SD method with the (μ, λ) ES (evolution strategy), is proposed, and is used for the evolutionary designing of larger sequential logic circuits. The proposed extrinsic EHW system is tested extensively on sequential logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library. The results demonstrate that 3SD–ES has much better performance in terms of scalability. It enables the evolutionary designing of larger sequential circuits than have ever been evolved before.

Keywords

Adaptive system Evolutionary computation Evolvable hardware Sequential circuit Decomposition 

Notes

Acknowledgments

This work is partly supported by the National Natural Science Foundation of China (No.60404004), and the 2006-2007 Excellent Young and Middle-aged Academic Leader Development Program of Anhui Province Research Experiment Bases. We are thankful to the anonymous reviewers for their valuable comments that help us to improve the quality of this paper.

References

  1. 1.
    A. Stoica, R. Andrei, Adaptive and evolvable hardware—a multifaceted analysis. In Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), (5–8 August 2007), pp. 486–498Google Scholar
  2. 2.
    X. Yao, T. Higuchi, Promises and challenges of evolvable hardware. IEEE Trans. Syst. Man Cybern C: Appl. Rev. 29(1), 87–97 (1999)CrossRefGoogle Scholar
  3. 3.
    J. Zhu, Y. Li, G. He, X. Xia, An intrinsic evolvable hardware based on multiplexer module array. In Proceedings of the 7th International Conference on Evolvable Systems: From Biology to Hardware (ICES 2007), vol. 4684 (Wuhan, China, 21–23 September 2007), pp. 35–44Google Scholar
  4. 4.
    V.K. Vassilev, D. Job, J. F. Miller, Towards the automatic design of more efficient digital circuits. In Proceedings of the Second NASA/DoD workshop on Evolvable Hardware (Palo Alto, California, 2000), pp. 151–160Google Scholar
  5. 5.
    J.F. Miller, P. Thomson, Discovering novel digital circuits using evolutionary techniques. In Proceedings of IEE Colloquium on Evolvable Systems, vol. 3 (3 March 1998) Google Scholar
  6. 6.
    J.F. Miller, P. Thomson, T. Fogarty, Designing electronic circuits using evolutionary algorithms. Arithmetic circuits: a case study. Genet. Algorithm. Evol. Strateg. Eng. Comput. Sci. 10, 105–131 (1997)Google Scholar
  7. 7.
    E. Stomeo, T. Kalganova, C. Lambert, Generalized disjunction decomposition for evolvable hardware. IEEE Trans. Syst. Man Cybern. Part B 36(5), 1024–1043 (2006)CrossRefGoogle Scholar
  8. 8.
    A.T. Soliman, H.M. Abbas, Synchronous sequential circuits design using evolutionary algorithms. In Proceedings of Electrical and Computer Engineering, vol. 4 (2–5 May 2004), pp. 2013–2016Google Scholar
  9. 9.
    T. Kalganova, J.F. Miller, Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness. In Proceedings of the First NASA/DoD Workshop on Evolvable Hardware (EH′99) (Pasadena, California, 1999), pp. 54–63Google Scholar
  10. 10.
    C.A. Coello Coello, A.D. Christiansen, A. Hernández Aguirre, Automated design of combinational logic circuits using genetic algorithms. In Proceedings of the International Conference on Artificial Neural Nets and Genetic Algorithms (ICANNGA ‘97) (1997), pp. 335–338Google Scholar
  11. 11.
    A.T. Soliman, H.M. Abbas, Combinational circuit design using evolutionary algorithms. In Proceedings IEEE Canadian Conference on Electrical ond Computer Engineering (CCECE 2003) vol. 1 (Montreal, Canada, 4–7 May 2003), pp. 251–254Google Scholar
  12. 12.
    B. Ali, A.E.A. Almaini, T. Kalganova, Evolutionary Algorithms and Their Use in the Design of Sequential Logic Circuits. Genet. Program Evol. Mach. 5(1), 11–29 (2004)CrossRefGoogle Scholar
  13. 13.
    A. Djupdal, P.C. Haddow, Evolving redundant structures for reliable circuits—lessons learned. In Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), (5–8 August 2007), pp. 455–462Google Scholar
  14. 14.
    G.W. Greenwood, Attaining fault tolerance through self-adaption: the strengths and weaknesses of evolvable hardware approaches. In Proceedings of the IEEE World Congress on Computational Intelligence (WCCI 2008), vol. 5050 (Hong Kong, China, 1–6 June 2008), pp. 368–387Google Scholar
  15. 15.
    Q. Ji, Y. Wang, M. Xie, J. Cui, Research on fault-tolerance of analog circuits based on evolvable hardware. In Proceedings of the 7th International Conference on Evolvable Systems: From Biology to Hardware (ICES 2007), vol. 4684 (Wuhan, China, 21–23 September 2007), pp. 100–108Google Scholar
  16. 16.
    Z. Vasicek, L. Sekanina, Hardware accelerators for cartesian genetic programming. In Proceedings of the 11th European Conference on Genetic Programming (EuroGP 2008), vol. 4971 (Naples, Italy, 26–28 March 2008), pp. 230–241Google Scholar
  17. 17.
    T. Kalganova, Bidirectional incremental evolution in extrinsic evolvable hardware. In Proceedings of the Second NASA/DoD Workshop on Evolvable Hardware (EH 2000) (Palo Alto, CA, USA, 13–15 July 2000), pp. 65–74Google Scholar
  18. 18.
    C.A. Coello Coello, A.D. Christiansen, A.H. Aguirre, Towards automated evolutionary design of combinational circuits. In Proceedings of the computers and electrical engineering, vol. 27 (30 November 2000), pp. 1–28Google Scholar
  19. 19.
    D. Jackson, Partitioned incremental evolution of hardware using genetic programming. In Proceedings of the 11th European Conference on Genetic Programming (EuroGP 2008), vol. 4971 (Naples, Italy, 26–28 March 2008), pp. 86–97Google Scholar
  20. 20.
    J.F. Miller, P. Thomson, Cartesian genetic programming. In Proceedings of the Third European Conference on Genetic Programming (Edinburgh, Berlin, 2000), pp. 121–132Google Scholar
  21. 21.
    O. Muntean, L. Diosan, M. Oltean. Solving the even-N-parity problems using best subtree genetic programming. In Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (5–8 August 2007), pp. 511–518Google Scholar
  22. 22.
    L. Sekanina. Evolutionary design of gate-level polymorphic digital circuits. In Proceedings of the Applications of Evolutionary Computing, vol. 3449 (Lausanne, Switzerland, 31 March 2005), pp. 185–194Google Scholar
  23. 23.
    E. Stomeo, T. Kalganova, C. Lambert, N. Lipnitsakya, Y. Yatskevich. On evolution of relatively large combinational logic circuits. In Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware (EH’05) (29 June –1 July 2005), pp. 59–66Google Scholar
  24. 24.
    P. Chongstitvatana, C. Aporntewan, Improving correctness of finite-state machine synthesis from multiple partial input/output sequences. In Proceedings of the First NASA/DoD Workshop on Evolvable Hardware (Pasadena, CA, USA, 19–21 July 1999), pp. 262–266Google Scholar
  25. 25.
    C. Manovit, C. Aporntewan, P. Chongstitvatana, Synthesis of synchronous sequential logic circuits from partial input/output sequences. In Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware, vol. 1478 (1998), pp. 98–105Google Scholar
  26. 26.
    C. Aporntewan, P. Chongstitvatana, An on-line evolvable hardware for learning finite-state machine. In Proceedings of International Conference on Intelligent Technologies (Bangkok, 13–15 December 2000) pp. 125–134Google Scholar
  27. 27.
    A.P. Shanthi, L. Karthik Singaram, Evolution of asynchronous sequential circuits. In Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware (29 June –1 July 2005), pp. 93–96Google Scholar
  28. 28.
    K. Slany, L. Sekanina, Fitness landscape analysis and image filter evolution using functional-level CGP. In Proceedings of the 10th European Conference on Genetic Programming, vol. 4445 (Valencia, Spain, 11–13 April 2007), pp. 311–320Google Scholar
  29. 29.
    T.G.W. Gordon, P.J. Bentley, Development brings scalability to hardware evolution. In Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware (EH’05) (29 June–1 July 2005), pp. 272–279Google Scholar
  30. 30.
    V.K. Vassilev, J.F. Miller, Scalability problems of digital circuit evolution evolvability and efficient designs. In Proceedings of the Second NASA/DoD workshop on Evolvable Hardware (Palo Alto, California, 2000), pp. 55–64Google Scholar
  31. 31.
    M. Hartmann, P.K. Lehre, P.C. Haddow, Evolved digital circuits and genome complexity. In Proceedings of the NASA/DoD Conference on Evolvable Hardware (EH’05) ( 29 June–1July 2005), pp. 79–86Google Scholar
  32. 32.
    T. Higuchi, M. Iwata, I. Kajitani, M. Murakawa, S. Yoshizawa, T. Furuya, Hardware evolution at gate and function levels. In Proceedings of the Biologically Inspired Autonomous Systems: Computation, Cognition and Action, Durham, North Carolina (March 1996)Google Scholar
  33. 33.
    M. Murakawa, S. Yoshizawa, I. Kajitani, T. Furuya, M. Iwata, T. Higuchi. Hardware evolution at function level. In Proceedings of the Fourth International Conference on Parallel Problem Solving from Nature, vol. 1141 (1996), pp. 62–71Google Scholar
  34. 34.
    J. Li, S. Huang, Adaptive salt-&-pepper noise removal: a function level evolution based approach. In Proceedings of the 2008 nasa/esa conference on adaptive hardware and systems (22–25 June 2008), pp. 391–397Google Scholar
  35. 35.
    J. Torresen, A divide-and-conquer approach to evolvable hardware. In Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware, vol. 1478 (1998), pp. 57–65Google Scholar
  36. 36.
    J. Wang, C.H. Piao, C.H. Lee, Implementing multi-VRC cores to evolve combinational logic circuits in parallel. In Proceedings of the 7th International Conference on Evolvable Systems: From Biology to Hardware (ICES 2007) vol. 4684 (Wuhan, China, 21–23 September 2007), pp. 23–34Google Scholar
  37. 37.
    D. Levi, Hereboy: A fast evolutionary algorithm. In Proceedings of the Second NASA/DoD Workshop on Evolvable Hardware (EH’00) (Palo Alto, CA, USA, 13–15 July 2000), pp. 17–24Google Scholar
  38. 38.
    J.C. Gallagher, S. Vigraham, G. Kramer, A family of compact genetic algorithms for intrinsic evolvable hardware. IEEE Trans. Evol. Comput. 8(2), 111–126 (2004)CrossRefGoogle Scholar
  39. 39.
    A.M. Tyrrell, R.A. Krohling, Y. Zhou, Evolutionary algorithm for the promotion of evolvable hardware. In Proceedings of Computers and Digital Techniques, vol. 151 (18 July 2004), pp. 267–275Google Scholar
  40. 40.
    T.G.W. Gordon, P.J. Bentley, Bias and scalability in evolutionary development. In Proceedings of the Genetic and Evolutionary Computation Conference (GECCO 2005) (25–29 June 2005), pp. 83–90Google Scholar
  41. 41.
    Sue-Hong Chow, Yi-Cheng Ho, Ting Ting Hwang, C.L. Liu, Low power realization of finite state machines-a decomposition approach. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 1(3), 315–340 (1996)CrossRefGoogle Scholar
  42. 42.
    L. Benini, G. De Micheli, E. Macii, Designing low-power circuits: practical recipes. IEEE Circuit. Syst. Mag. 1(1), 6–25 (2001)CrossRefGoogle Scholar
  43. 43.
    L. Benini, G. De Micheli, F. Vermeulen, Finite-state machine partioning for low power. In Proceedings of the International Symposium on Circuits and Systems, (1998), vol. 2, pp. 5–8Google Scholar
  44. 44.
    L. Yuan, G. Qu, T. Villa, A. Sangiovanni-Vincentelli, An FSM reengineering approach to sequential circuit synthesis by state splitting. IEEE Trans. Comput.-Aided Des. Integr. Circuit. Syst. 27(6), 1159–1164 (2008)CrossRefGoogle Scholar
  45. 45.
    S. Yang, Logic synthesis and optimisation benchmark user guide version 3.0 (Microelectronics Center of North Carolina, Research Triangle Park, 1991)Google Scholar
  46. 46.
    J. Bao, Y. Li, W. Mao, Digitial Logic (High Education Press, Beijing, 1997) (in Chinese)Google Scholar
  47. 47.
    E. Stomeo, T. Kalganova, C. Lambert, A novel genetic algorithm for evolvable hardware. In Proceedings of the 2006 IEEE Congress on Evolutionary Computation (Canada, 16–21 July 2006), pp. 134–141Google Scholar
  48. 48.
    M. Murakawa, S. Yoshizawa, T. Higuchi, Adaptive equalization of digital communication channels using evolvable hardware. In Proceedings of the First International Conference on Evolvable Systems: From Biology to Hardware, vol. 1259 (1996), pp. 377–389Google Scholar
  49. 49.
    A. Sumathi, R.S.D. Wahida Banu, Digital filter design using evolvable hardware chip for image enhancement. In Proceedings of the International Conference on Intelligent Computing, ICIC 2006, vol. 4113 (Kunming, China, 16–19 August 2006), pp. 663–671Google Scholar
  50. 50.
    A. Antola, M. Castagna, P. Gotti, M.D. Santambrogio. Evolvable Hardware: A functional level evolution framework based on impulse C. In Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA (Las Vegas, Nevada, USA, 25–28 June 2007), pp. 216–219Google Scholar
  51. 51.
    A. Stoica, D. Keymeulen, R. Zebulum, A. Thakoor, T. Daud, G. Klimeck, Y. Jin, R. Tawel, V. Duong, Evolution of analog circuits on field programmable transistor arrays. In Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware (2000), pp. 99–108Google Scholar
  52. 52.
    J. Langeheine, J. Becker, S. Foiling, K. Meier, J. Schemmel, A CMOS FPTA chip for intrinsic hardware evolution of analog electronic circuits. In Proceedings of the 3rd NASA/DoD Workshop on Evolvable Hardware (EH 2001) (Long Beach, CA, USA, 12–14 July 2001), pp. 172–175Google Scholar
  53. 53.
    M. Trefzer, J. Langeheine, K. Meier, J. Schemmel, A modular framework for the evolution of circuits on configurable transistor array architectures. In Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems (2006), pp. 32–42Google Scholar
  54. 54.
    J. Wang, Q.S. Chen, C.H. Lee, Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware. Comput. Digit. Tech. IET 2(5), 386–400 (2008)CrossRefGoogle Scholar
  55. 55.
    T. Higuchi, M. Iwata, D. Keymeulen, H. Sakanashi, M. Murakawa, I. Kajitani, E. Takahashi, K. Toda, M. Salami, N. Kajihara, N. Otsu, Real-world applications of analog and digital evolvable hardware. IEEE Trans. Evol. Comput. 3(3), 220–235 (1999)CrossRefGoogle Scholar
  56. 56.
    L. Sekanina, Towards evolvable IP cores for FPGAs. In Proceedings of NASA/DoD Conference on Evolvable Hardware (9–11 July 2003)Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.Nature Inspired Computation and Applications Laboratory (NICAL), Department of Computer Science and TechnologyUniversity of Science and Technology of ChinaHefeiChina
  2. 2.Anhui Key Laboratory of Software in Computing and CommunicationUniversity of Science and Technology of ChinaHefeiChina

Personalised recommendations