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Formal Methods in System Design

, Volume 50, Issue 2–3, pp 317–352 | Cite as

Symbolic trajectory evaluation for word-level verification: theory and implementation

  • Supratik ChakrabortyEmail author
  • Zurab Khasidashvili
  • Carl-Johan H. Seger
  • Rajkumar Gajavelly
  • Tanmay Haldankar
  • Dinesh Chhatani
  • Rakesh Mistry
Article

Abstract

Symbolic trajectory evaluation (STE) is a model checking technique that has been successfully used to verify many industrial designs. Existing implementations of STE reason at the level of bits, allowing signals in a circuit to take values from a lattice comprised of three elements: 0, 1, and X. This limits the amount of abstraction that can be achieved, and presents limitations to scaling STE to even larger designs. The main contribution of this paper is to show how much more abstract lattices can be derived automatically from register-transfer level descriptions, and how a model checker for the general theory of STE instantiated with such abstract lattices can be implemented in practice. We discuss several implementation issues, including how word-level circuits can be symbolically simulated using a new encoding for words that allows representing X values of sub-words succinctly. This gives us the first practical word-level STE engine, called \(\mathsf {STEWord}\). Experiments on a set of designs similar to those used in industry show that \(\mathsf {STEWord}\) scales better than bit-level STE, as well as word-level bounded model checking.

Keywords

Symbolic trajectory evaluation Word-level verification SMT solving X-based abstraction Hardware verification RTL verification Invalid-bit encoding Symbolic simulation 

Notes

Acknowledgements

We thank Taly Hocherman and Dan Jacobi for their help and advice in designing a SystemVerilog symbolic simulator. We thank Ashutosh Kulkarni and Soumyajit Dey for their help in implementing and debugging \(\mathsf {STEWord}\). Rajkumar Gajavelly, Tanmay Haldankar, Dinesh Chhatani and Rakesh Mistry were supported by a research grant from Intel Corporation, which is gratefully acknowledged. Funding was provided by Intel Corporation as a research grant to IIT Bombay.

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Copyright information

© Springer Science+Business Media New York 2017

Authors and Affiliations

  1. 1.Department of Computer Science and EngineeringIIT BombayMumbaiIndia
  2. 2.Intel IDCHaifaIsrael
  3. 3.Department of Computer Science and EngineeringChalmers University of TechnologyGothenburgSweden

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