Formal Methods in System Design

, Volume 48, Issue 1–2, pp 1–45 | Cite as

Causality problem in real-time calculus

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Abstract

Real-time calculus (RTC) (Thiele et al. in: ISCAS, Geneva, 2000) is a framework to analyze heterogeneous, real-time systems that process event streams of data. The streams are characterized by pairs of curves, called arrival curves, that express upper and lower bounds on the number of events that may arrive over any specified time interval. A well-known limitation of RTC is that it cannot model systems with states and several works (Altisen and Moy in: ECRTS, Brussels, http://www-verimag.imag.fr/~moy/publications/ac2lus-conf, 2010; Altisen et al. in: QAPL, Paphos, http://www-verimag.imag.fr/~moy/publications/gran-paper, 2010; Banerjee and Dasgupta in: Proceedings of the conference on design, automation & test in Europe, 2014; Giannopoulou et al. in: Proceedings of the tenth ACM international conference on embedded software, New York, 2012; Krcál et al. in: Proceedings of 19th Nordic workshop on programming theory (NWPT07), Oslo, 2007; Kumar et al. in: Proceedings of the 49th annual design automation conference, New York, 2012; Lampka et al. in: EMSOFT, Grenoble, 2009; Lampka et al. in Des Autom Embed Syst 14:1–35, 2010; Perathoner et al. in: DATE, IEEE, Grenoble, 2013; Lampka et al. in Int J Softw Tools Technol Transf 15:155–170, 2011; Phan et al. in: Proceedings of the IEEE real-time systems symposium (RTSS), Los Alamitos, doi:10.1109/RTSS.2007.46, 2007; Uppsala University in Cats tool, Uppsala University, Uppsala, 2007) studied how to interface RTC curves with state-based models. Doing so, while trying, for example to generate a stream of events that satisfies some given pair of curves, we faced a causality problem (Raymond in Compilation efficace d’un langage declaratif synchrone: Le generateur de code Lustre-v3, PhD thesis, 1991): it can be the case that, after generating a finite prefix of an event stream, the generator deadlocks, since no extension of the prefix can satisfy the curves afterwards. This paper formally defines the problem; it states and proves algebraic results that characterize causal pairs of curves, i.e. curves for which the problem cannot occur. We consider the general case of infinite curve models, either discrete or continuous time and events. The paper provides an analysis on how causality issues appear when using arrival curves and how they could be handled. It also provides an overview of algorithms to compute causal curves in several models. These algorithms compute a canonical representation of a pair of curves, which is the best pair of curves among the curves equivalent to the ones they take as input.

Keywords

Real-time calculus Arrival curve Causality Modular-performance analysis Forbidden regions 

References

  1. 1.
    Altisen K, Moy M (2010) ac2lus: Bringing SMT-solving and abstract interpretation techniques to real-time calculus through the synchronous language Lustre. In: ECRTS, Brussels, Belgium. http://www-verimag.imag.fr/~moy/publications/ac2lus-conf
  2. 2.
    Moy M, Altisen K (2010) Arrival curves for real-time calculus: the causality problem and its solutions. In: Esparza J, Majumdar R (eds) Tools and algorithms for the construction and analysis of systems. Springer, Berlin, pp 358–372Google Scholar
  3. 3.
    Altisen K, Moy M (2011) Causality closure for a new class of curves in real-time calculus. In: Proceedings of the 1st international workshop on worst-case traversal time, ACM, Vienna, pp 3–10. doi:10.1145/2071589.2071590. http://www-verimag.imag.fr/~moy/publications/wctt2011
  4. 4.
    Altisen K, Liu Y, Moy M (2010) Performance evaluation of components using a granularity-based interface between real-time calculus and timed automata. In: QAPL, Paphos. http://www-verimag.imag.fr/~moy/publications/gran-paper
  5. 5.
    Banerjee K, Dasgupta P (2014) Acceptance and random generation of event sequences under real time calculus constraints. In: Proceedings of the conference on design, automation & test in Europe. European Design and Automation Association, p 254Google Scholar
  6. 6.
    Bouillard A, Thierry É (2008) An algorithmic toolbox for network calculus. Discret Event Dyn Syst 18(1):3–49MathSciNetCrossRefMATHGoogle Scholar
  7. 7.
    Bouillard A, Cottenceau B, Gaujal B, Hardouin L, Lagrange S, Lhommeau M, Thierry E (2009a) COINC library: a toolbox for network calculus. In: Fourth international conference on performance evaluation methodologies and tools, valuetools, Pisa. https://hal.inria.fr/hal-00788929
  8. 8.
    Bouillard A, Jouhet L, Thierry E (2009b) Service curves in network calculus: dos and don’ts. Research peport RR-7094, INRIA. http://hal.inria.fr/inria-00431674/en/
  9. 9.
    Chakraborty S, Künzli S, Thiele L (2003) A general framework for analysing system properties in platform-based embedded system designs. In: DATE, Citeseer, vol 3, p 10190Google Scholar
  10. 10.
    Ghosh S, Dasgupta P (2015) Formal methods for pattern based reliability analysis in embedded systems. In: Proceedings of the 2015 IEEE 28th international conference on VLSI design (VLSID), pp 192–197Google Scholar
  11. 11.
    Giannopoulou G, Lampka K, Stoimenov N, Thiele L (2012) Timed model checking with abstractions: towards worst-case response time analysis in resource-sharing manycore systems. In: Proceedings of the tenth ACM international conference on embedded software, ACM, New York, pp 63–72Google Scholar
  12. 12.
    Guan N, Yi W (2013) Finitary real-time calculus: efficient performance analysis of distributed embedded systems. In: Proceedings of the 2013 IEEE 34th real-time systems symposium (RTSS), pp 330–339Google Scholar
  13. 13.
    Hagen G, Tinelli C (2008) Scaling up the formal verification of Lustre programs with SMT-based techniques. In: Cimatti A, Jones R (eds) FMCAD. IEEE, Portland, pp 109–117. ftp://ftp.cs.uiowa.edu/pub/tinelli/papers/HagTin-FMCAD-08.pdf
  14. 14.
    Halbwachs N, Lagnier F, Ratel C (1992) Programming and verifying critical systems by means of the synchronous data-flow programming language lustre. IEEE Trans Softw Eng 18(9):785–793CrossRefMATHGoogle Scholar
  15. 15.
    Henzinger TA, Nicollin X, Sifakis J, Yovine S (1992) Symbolic model checking for real-time systems. Inf Comput 111:394–406MathSciNetMATHGoogle Scholar
  16. 16.
    Jeannet B (2003) Dynamic partitioning in linear relation analysis. Application to the verification of reactive systems. Formal Methods Syst Des 23(1):5–37CrossRefMATHGoogle Scholar
  17. 17.
    Jonsson B, Perathoner S, Thiele L, Yi W (2008) Cyclic dependencies in modular performance analysis. In: EMSOFT. doi:10.1145/1450058.1450083
  18. 18.
    Krcál P, Mokrushin L, Yi W (2007) A tool for compositional analysis of timed systems by abstraction. In: Proceedings of 19th Nordic workshop on programming theory (NWPT07), OsloGoogle Scholar
  19. 19.
    Kumar P, Goswami D, Chakraborty S, Annaswamy A, Lampka K, Thiele L (2012) A hybrid approach to cyber-physical systems verification. In: Proceedings of the 49th annual design automation conference, ACM, New York, pp 688–696Google Scholar
  20. 20.
    Künzli S, Thiele L (2006) Generating event traces based on arrival curves. In: Conference on measurement, modeling, and evaluation of computer and communication systems (MMB), VDE Verlag, pp 81–98Google Scholar
  21. 21.
    Künzli S, Poletti F, Benini L, Thiele L (2006) Combining simulation and formal methods for system-level performance analysis. In: DATE, 3001 Leuven, Belgium, pp 236–241Google Scholar
  22. 22.
    Lampka K, Perathoner S, Thiele L (2009) Analytic real-time analysis and timed automata: a hybrid method for analyzing embedded real-time systems. In: Chakraborty S, Halbwachs N (eds) Proceedings of the 9th ACM & IEEE international conference on Embedded software, EMSOFT 2009, Grenoble, France, October 12–16, ACM, New York, pp 107–116Google Scholar
  23. 23.
    Lampka K, Perathoner S, Thiele L (2010) Analytic real-time analysis and timed automata: a hybrid methodology for the performance analysis of embedded real-time systems. Des Autom Embed Syst 14(3):1–35CrossRefGoogle Scholar
  24. 24.
    Lampka K, Perathoner S, Thiele L (2013) Component-based system design: analytic real-time interfaces for state-based component implementations. Int J Softw Tools Technol Transf 15(3):155–170CrossRefGoogle Scholar
  25. 25.
    Le Boudec JY, Thiran P (2001) Network calculus. Springer, Berlin. http://infoscience.epfl.ch/getfile.py?recid=282&mode=best
  26. 26.
    Lin CW, Di Natale M, Zeng H, Phan LTX, Sangiovanni-Vincentelli A (2013) Timing analysis of process graphs with finite communication buffers. In: Proceedings of the 2013 IEEE 19th real-time and embedded technology and applications symposium (RTAS), pp 227–236Google Scholar
  27. 27.
    Liu CL, Layland JW (1973) Scheduling algorithms for multiprogramming in a hard-real-time environment. J ACM 20(1):46–61MathSciNetCrossRefMATHGoogle Scholar
  28. 28.
    Moy M, Altisen K (2009) Arrival curves for real-time calculus: the causality problem and its solutions. Technical report TR-2009-15, VerimagGoogle Scholar
  29. 29.
    Moy M, Altisen K (2011) Causality closure for a new class of curves in real-time calculus full version. Technical report TR-2011-13, Verimag Research ReportGoogle Scholar
  30. 30.
    Perathoner S, Lampka K, Thiele L (2011) Composing heterogeneous components for system-wide performance analysis. In: DATE, IEEE, pp 842–847Google Scholar
  31. 31.
    Phan LT, Chakraborty S, Thiagarajan P, Thiele L (2007) Composing functional and state-based performance models for analyzing heterogeneous real-time systems. In: Proceedings of the IEEE real-time systems symposium (RTSS), IEEE Computer Society, Los Alamitos, CA, pp 343–352. doi:10.1109/RTSS.2007.46
  32. 32.
    QComputer Engineering and Networks Laboratory (TIK), ETH Zurich, Switzerland (2008) Modular performance analysis with real-time calculus. Software Toolbox. http://www.mpa.ethz.ch/
  33. 33.
    Raymond P (1991) Compilation efficace d’un langage declaratif synchrone: Le generateur de code Lustre-v3. PhD thesis, Institut National Polytechnique de Grenoble - INPG, section 13.7, “Causalité”, pp 119–123Google Scholar
  34. 34.
    Raymond P (2000) Lustre v4 manual. Verimag, GieresGoogle Scholar
  35. 35.
    Schranzhofer A, Pellizzoni R, Chen JJ, Thiele L, Caccamo M (2011) Timing analysis for resource access interference on adaptive resource arbiters. In: Proceedings of the 17th IEEE real-time and embedded technology and applications symposium (RTAS 2011), pp 213–222Google Scholar
  36. 36.
    Simalatsar A, Ramadian Y, Lampka K, Perathoner S, Passerone R, Thiele L (2011) Enabling parametric feasibility analysis in real-time calculus driven performance evaluation. In: Proceedings of the 2011 international conference on compilers, architecture, and synthesis for embedded systems, CASES 2011. ACM, Taipei, pp 155–164Google Scholar
  37. 37.
    Thiele L, Chakraborty S, Naedele M (2000) Real-time calculus for scheduling hard real-time systems. In: International Symposium on Circuits and Systems (ISCAS), Geneva, Switzerland, March 2000, vol 4, pp 101–104Google Scholar
  38. 38.
    Uppsala University (2007) Cats tool. Uppsala University, Uppsala. http://www.timestool.com/cats
  39. 39.
    Wandeler E (2006) Modular performance analysis and interface-based design for embedded real-time systems. PhD thesis, ETH ZurichGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  1. 1.Univ. Grenoble Alpes, VERIMAGGrenobleFrance
  2. 2.CNRS, VERIMAGGrenobleFrance

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