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Formal Methods in System Design

, Volume 41, Issue 3, pp 236–268 | Cite as

Optimized temporal monitors for SystemC

  • Deian TabakovEmail author
  • Kristin Y. Rozier
  • Moshe Y. Vardi
Article

Abstract

SystemC is a modeling language built as an extension of C++. Its growing popularity and the increasing complexity of designs have motivated research efforts aimed at the verification of SystemC models using assertion-based verification (ABV), where the designer asserts properties that capture the design intent in a formal language such as PSL or SVA. The model then can be verified against the properties using runtime or formal verification techniques. In this paper we focus on automated generation of runtime monitors from temporal properties. Our focus is on minimizing runtime overhead, rather than monitor size or monitor-generation time. We identify four issues in monitor generation: state minimization, alphabet representation, alphabet minimization, and monitor encoding. We conduct extensive experimentation and identify a combination of settings that offers the best performance in terms of runtime overhead.

Keywords

SystemC Assertion checkers Monitors Testing 

Notes

Acknowledgements

We thank Alexandre Duret-Lutz for his code patch replacing the functionality of spot::prune_scc, which we used to upgrade from SPOT 0.4, used in the experiments executed on Ada, to SPOT 0.7.1 used in the experiments executed on SUG@R. We also thank Patrick Meredith and Dmitry Korchemny for suggesting that we consider table look-up encodings. Finally, we thank the anonymous reviewers for their comments and feedback.

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Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  • Deian Tabakov
    • 1
    Email author
  • Kristin Y. Rozier
    • 2
  • Moshe Y. Vardi
    • 3
  1. 1.Schlumberger Information SolutionsHoustonUSA
  2. 2.NASA Ames Research CenterMoffett FieldUSA
  3. 3.Rice UniversityHoustonUSA

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