Formal Methods in System Design

, Volume 40, Issue 2, pp 170–205 | Cite as

Fences in weak memory models (extended version)

  • Jade Alglave
  • Luc Maranget
  • Susmit Sarkar
  • Peter Sewell


We present a class of relaxed memory models, defined in Coq, parameterised by the chosen permitted local reorderings of reads and writes, and by the visibility of inter- and intra-processor communications through memory (e.g. store atomicity relaxation). We prove results on the required behaviour and placement of memory fences to restore a given model (such as Sequential Consistency) from a weaker one. Based on this class of models we develop a tool, diy, that systematically and automatically generates and runs litmus tests. These tests can be used to explore the behaviour of processor implementations and the behaviour of models, and hence to compare the two against each other. We detail the results of experiments on Power and a model we base on them.


Weak memory models Formal proofs Testing tool PowerPC Generic framework Fences 



We thank Damien Doligez and Xavier Leroy for invaluable discussions and comments, Assia Mahboubi and Vincent Siles for advice on the Coq development, Thomas Braibant, Jules Villard and Boris Yakobowski for comments on a draft, and the anonymous referees for comments on the presentation. We thank the HPCx (UK) and IDRIS(.fr) high-performance computing services. We acknowledge support from EPSRC grants EP/F036345, EP/H005633, and EP/H027351/1, and ANR grant ANR-06-SETI-010-02.


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Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  • Jade Alglave
    • 1
    • 3
  • Luc Maranget
    • 1
  • Susmit Sarkar
    • 2
  • Peter Sewell
    • 2
  1. 1.INRIARocquencourtFrance
  2. 2.University of CambridgeCambridgeUK
  3. 3.Oxford UniversityOxfordUK

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