Formal Methods in System Design

, Volume 35, Issue 1, pp 56–72

Word level bitwidth reduction for unbounded hardware model checking

Article

Abstract

In this paper we present a word-level model checking method that attempts to speed up safety property checking of industrial netlists. Our aim is to construct an algorithm that allows us to check both bounded and unbounded properties using standard bit-level model checking methods as back-end decision procedures, while incurring minimum runtime penalties for designs that are unsuited to our analysis. We do this by combining modifications of several previously known techniques into a static abstraction algorithm which is guaranteed to produce bit-level netlists that are as small or smaller than the original bitblasted designs. We evaluate our algorithm on several challenging hardware components.

Keywords

Word level Model checking Static analysis Formal methods 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.Synopsys Inc.HillsboroUSA

Personalised recommendations