Formal Methods in System Design

, Volume 34, Issue 1, pp 59–81 | Cite as

Timed verification of the generic architecture of a memory circuit using parametric timed automata

  • Remy Chevallier
  • Emmanuelle Encrenaz-Tiphene
  • Laurent FribourgEmail author
  • Weiwen Xu


Using a variant of Clariso-Cortadella’s parametric method for verifying asynchronous circuits, we analyse some crucial timing behaviors of the architecture of SPSMALL memory, a commercial product of STMicroelectronics. Using the model of parametric timed automata and model checker HYTECH, we formally derive a set of linear constraints that ensure the correctness of the response times of the memory. We are also able to infer the constraints characterizing the optimal setup timings of input signals. We have checked, for two different implementations of this architecture, that the values given by our model match remarkably with the values obtained by the designer through electrical simulation.


Memory circuit Timed automata Model checking 


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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Remy Chevallier
    • 1
  • Emmanuelle Encrenaz-Tiphene
    • 2
  • Laurent Fribourg
    • 2
    Email author
  • Weiwen Xu
    • 2
  1. 1.STMicroelectronics, FTM, Central R&DCrollesFrance
  2. 2.LSV-CNRS, ENS de CachanCachanFrance

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