Journal of Electronic Testing

, Volume 20, Issue 6, pp 575–589 | Cite as

Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation

  • Zainalabedin Navabi
  • Shahrzad Mirkhani
  • Meisam Lavasani
  • Fabrizio Lombardi


This paper presents a novel fault simulation environment in VHDL. By writing a library of special fault simulation models, a traditional model is transformed into a new model that performs fault simulation using a VHDL simulation engine. Pre- and post-synthesis VHDL models are used for an effective implementation, better performance and to minimize the overhead associated with VHDL simulation. Models are written such that an automatic switching mechanism selects gate level descriptions for originating faults and behavioral descriptions for propagating them.

hierarchical fault simulation mixed level register transfer level VHDL delta times 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer Science+Business Media, Inc. 2004

Authors and Affiliations

  1. 1.Electrical and Computer EngineeringUniversity of TehranIran
  2. 2.Electrical and Computer EngineeringNortheastern UniversityUSA

Personalised recommendations